Abstract: Provided is a semiconductor device capable of adjusting an internal voltage after the internal voltage is raised. An internal voltage raising circuit of a flash memory includes: an internal voltage generation circuit for generating an internal voltage based on a power supply voltage supplied from outside; a determination circuit for comparing the internal voltage with a reference voltage and generating an enablement signal when detecting that the internal voltage is greater than the reference voltage; and an internal circuit operable in response to the enablement signal. In response to the generation of the enablement signal, the determination circuit lowers the reference voltage to increase a difference between the reference voltage and the internal voltage, and prevents the enablement signal from being disabled during subsequent trimming of the internal voltage.

Abstract: Provided is a semiconductor device capable of adjusting an internal voltage after the internal voltage is raised. An internal voltage raising circuit of a flash memory includes: an internal voltage generation circuit for generating an internal voltage based on a power supply voltage supplied from outside; a determination circuit for comparing the internal voltage with a reference voltage and generating an enablement signal when detecting that the internal voltage is greater than the reference voltage; and an internal circuit operable in response to the enablement signal. In response to the generation of the enablement signal, the determination circuit lowers the reference voltage to increase a difference between the reference voltage and the internal voltage, and prevents the enablement signal from being disabled during subsequent trimming of the internal voltage.

Abstract: A semiconductor device includes memory blocks MB1 and MB2 and redundancy determination circuit 25 that can enter a normal operation mode that accesses either memory block MB1 or memory block MB2 and a refresh mode that simultaneously accesses both memory block MB1 and memory block MB2. In response to normal memory cell NMC that belongs to at least one of memory blocks MB1 and MB2 being replaced by redundant memory cell RMC in the refresh mode, redundancy determination circuit 25 deactivates normal cell area NCA to which normal memory cell NMC that is a source of replacement belongs, and activates redundant cell area RCA to which redundant memory cell RMC that is to be replaced belongs and normal cell area NCA to which normal memory cell NMC that is not being replaced belongs.

Abstract: Disclosed herein is a device that includes: a set of address terminals supplied with a set of address signals, each of the address signals being changed in logic level; memory mats to which address ranges are allocated, respectively, the address ranges being different from each other, each of the memory mats including memory cells; and decoder units each provided correspondingly to corresponding memory mat. Each of the decoder units includes a set of first input nodes and a set of second input nodes, the set of first input nodes of each of the decoder units being coupled to the set of address terminals to receive the set of address signals, the set of second input nodes of each of the decoder units being coupled to receive an associated one of sets of control signals, each of the control signals being fixed in logic level.

Abstract: A semiconductor device includes memory blocks MB1 and MB2 and redundancy determination circuit 25 that can enter a normal operation mode that accesses either memory block MB1 or memory block MB2 and a refresh mode that simultaneously accesses both memory block MB1 and memory block MB2. In response to normal memory cell NMC that belongs to at least one of memory blocks MB1 and MB2 being replaced by redundant memory cell RMC in the refresh mode, redundancy determination circuit 25 deactivates normal cell area NCA to which normal memory cell NMC that is a source of replacement belongs, and activates redundant cell area RCA to which redundant memory cell RMC that is to be replaced belongs and normal cell area NCA to which normal memory cell NMC that is not being replaced belongs.

Abstract: A semiconductor device includes a first amplifier circuit, a second amplifier circuit, first and second bit lines coupled to the first amplifier circuit, third and fourth bit lines coupled to the second amplifier circuit, a first equalizer circuit being coupled to the first and second bit lines, and a second equalizer circuit being coupled between the second and third bit lines. The second equalizer circuit being closer to the second amplifier circuit than the first equalizer circuit, the first equalizer circuit being closer to the first amplifier circuit than the second equalizer circuit.

Abstract: A semiconductor device includes a voltage step-up circuit and a control circuit. The voltage step-up circuit includes at least a first capacitor and a second capacitor which generate an internal power supply voltage. The control circuit controls the voltage step-up circuit. The control circuit connects the first and second capacitors in series to perform a first voltage step-up operation and connects the first and second capacitors in parallel to perform a second voltage step-up operation. The voltage step-up circuit generates a first stepped-up voltage in the first voltage step-up operation and generates a second stepped-up voltage in the second voltage step-up operation. The circuit area of the voltage step-up circuit with a plurality of stepped-up levels is reduced.

Abstract: A calibration circuit includes: a replica buffer that drives a calibration terminal ZQ; a reference voltage generating circuit that generates a reference voltage VMID; a comparing circuit that compares a voltage appearing in the calibration terminal ZQ with the reference voltage VMID; an impedance adjusting circuit that changes an output impedance of the replica buffer based on a result of comparison carried out by the comparing circuit; and a reference voltage adjusting circuit that adjusts the reference voltage VMID. With this arrangement, the reference voltage VMID can be offset by taking into account a resistance component present between the calibration terminal ZQ and the external terminal, and therefore, a more accurate calibration operation can be carried out.

Abstract: A semiconductor memory chip with an On-Die Termination (ODT) function is disclosed, which comprises a delay locked loop (DLL) circuit, a synchronous circuit, an asynchronous circuit, a select signal generator, and a selector. The DLL circuit is configured to produce a local clock signal in response to a clock signal when a clock enable (CKE) signal is asserted. The DLL circuit has a predetermined boost time. The select signal generator is configured to assert a select signal in consideration of the predetermined boost time. The selector is configured to select an output of the asynchronous circuit until the select signal is asserted but to select another output of the synchronous circuit after the select signal is asserted.

Abstract: A semiconductor device includes a voltage step-up circuit and a control circuit. The voltage step-up circuit includes at least a first capacitor and a second capacitor which generate an internal power supply voltage. The control circuit controls the voltage step-up circuit. The control circuit connects the first and second capacitors in series to perform a first voltage step-up operation and connects the first and second capacitors in parallel to perform a second voltage step-up operation. The voltage step-up circuit generates a first stepped-up voltage in the first voltage step-up operation and generates a second stepped-up voltage in the second voltage step-up operation. The circuit area of the voltage step-up circuit with a plurality of stepped-up levels is reduced.

Abstract: A calibration circuit includes: a replica buffer that drives a calibration terminal ZQ; a reference voltage generating circuit that generates a reference voltage VMID; a comparing circuit that compares a voltage appearing in the calibration terminal ZQ with the reference voltage VMID; an impedance adjusting circuit that changes an output impedance of the replica buffer based on a result of comparison carried out by the comparing circuit; and a reference voltage adjusting circuit that adjusts the reference voltage VMID. With this arrangement, the reference voltage VMID can be offset by taking into account a resistance component present between the calibration terminal ZQ and the external terminal, and therefore, a more accurate calibration operation can be carried out.

Abstract: A semiconductor memory chip with an On-Die Termination (ODT) function is disclosed, which comprises a delay locked loop (DLL) circuit, a synchronous circuit, an asynchronous circuit, a select signal generator, and a selector. The DLL circuit is configured to produce a local clock signal in response to a clock signal when a clock enable (CKE) signal is asserted. The DLL circuit has a predetermined boost time. The select signal generator is configured to assert a select signal in consideration of the predetermined boost time. The selector is configured to select an output of the asynchronous circuit until the select signal is asserted but to select another output of the synchronous circuit after the select signal is asserted.