Patents by Inventor Yuki Imoto

Yuki Imoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959165
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsunori Maruyama, Yuki Imoto, Hitomi Sato, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Takashi Shimazu
  • Publication number: 20230094969
    Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.
    Type: Application
    Filed: December 2, 2022
    Publication date: March 30, 2023
    Inventors: Junichiro SAKATA, Tetsunori MARUYAMA, Yuki IMOTO
  • Patent number: 11545579
    Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: January 3, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Tetsunori Maruyama, Yuki Imoto
  • Publication number: 20220117532
    Abstract: An oral cavity sensor that includes a sensor portion having a flexible first resin layer and a pair of electrode portions on the flexible first resin layer and configured to measure pressure; and a flexible second resin layer covering the pair of electrode portions, wherein the flexible first resin layer is softer than the flexible second resin layer.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 21, 2022
    Inventors: Jun TAKAGI, Yuki IMOTO, Tomoki TAKAHASHI
  • Publication number: 20220037532
    Abstract: A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.
    Type: Application
    Filed: October 19, 2021
    Publication date: February 3, 2022
    Inventors: Satoshi TORIUMI, Takashi HAMADA, Tetsunori MARUYAMA, Yuki IMOTO, Yuji ASANO, Ryunosuke HONDA, Shunpei YAMAZAKI
  • Patent number: 11217703
    Abstract: A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: January 4, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Takashi Hamada, Tetsunori Maruyama, Yuki Imoto, Yuji Asano, Ryunosuke Honda, Shunpei Yamazaki
  • Patent number: 11105453
    Abstract: A pipe coupling member is configured to prevent a coil spring from being plastically deformed or dislodged from a coupling body even when a force acts on a valve element. The pipe coupling member includes a coupling body having a fluid passage, a valve element displaceable in the fluid passage, and a coil spring configured to urge the valve element toward a closed position. The coil spring is formed by helically winding a wire and has a fitting portion fitted and secured in a spring fitting groove, a locking portion contiguous with the fitting portion and having an outer diameter larger than an inner diameter of the fitting portion when fitted in the spring fitting groove, a valve support portion supporting the valve element, and an expanding-contracting portion extending between the locking portion and the valve support portion to expand and contract.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 31, 2021
    Assignee: NITTO KOHKI CO., LTD.
    Inventor: Yuki Imoto
  • Publication number: 20210230740
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Tetsunori MARUYAMA, Yuki IMOTO, Hitomi SATO, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Takashi SHIMAZU
  • Patent number: 11066739
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsunori Maruyama, Yuki Imoto, Hitomi Sato, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Takashi Shimazu
  • Publication number: 20210036160
    Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.
    Type: Application
    Filed: October 9, 2020
    Publication date: February 4, 2021
    Inventors: Junichiro SAKATA, Tetsunori MARUYAMA, Yuki IMOTO
  • Patent number: 10889888
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: January 12, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsunori Maruyama, Yuki Imoto, Hitomi Sato, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Takashi Shimazu
  • Publication number: 20200357925
    Abstract: A minute transistor is provided. A semiconductor device includes a semiconductor over a substrate, a first conductor and a second conductor over the semiconductor, a first insulator over the first conductor and the second conductor, a second insulator over the semiconductor, a third insulator over the second insulator, and a third conductor over the third insulator. The third insulator is in contact with a side surface of the first insulator. The semiconductor includes a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. The length between a top surface of the semiconductor and the bottom surface of the third conductor is longer than the length between the first region and the third region.
    Type: Application
    Filed: June 18, 2020
    Publication date: November 12, 2020
    Inventors: Satoshi TORIUMI, Takashi HAMADA, Tetsunori MARUYAMA, Yuki IMOTO, Yuji ASANO, Ryunosuke HONDA, Shunpei YAMAZAKI
  • Patent number: 10804409
    Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: October 13, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Tetsunori Maruyama, Yuki Imoto
  • Patent number: 10693013
    Abstract: A minute transistor with low parasitic capacitance, high frequency characteristics, favorable electrical characteristics, stable electrical characteristics, and low off-state current is provided. A semiconductor device includes a semiconductor over a substrate, a source and a drain over the semiconductor, a first insulator over the source and the drain, a second insulator over the semiconductor, a third insulator in contact with a side surface of the first insulator and over the second insulator, and a gate over the third insulator. The semiconductor includes a first region overlapping with the source, a second region overlapping with the drain, and a third region overlapping with the gate. The length between a top surface of the third region of the semiconductor and a bottom surface of the gate is longer than the length between the first region and the third region.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 23, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Takashi Hamada, Tetsunori Maruyama, Yuki Imoto, Yuji Asano, Ryunosuke Honda, Shunpei Yamazaki
  • Publication number: 20200119199
    Abstract: A semiconductor device having favorable characteristics is provided. In a semiconductor device including a transistor, the transistor includes a first oxide, a second oxide over the first oxide, an insulator over the second oxide, and a conductor over the insulator. The first oxide includes a channel formation region and a first region and a second region positioned so that the channel formation region is sandwiched therebetween. The second oxide is provided so as to be in contact with the channel formation region, part of the first region, and part of the second region. The first region and the second region have lower concentrations of oxygen than the channel formation region.
    Type: Application
    Filed: May 15, 2018
    Publication date: April 16, 2020
    Inventors: Shunpei YAMAZAKI, Naoki OKUNO, Yuta ENDO, Yuki IMOTO
  • Patent number: 10415734
    Abstract: A female pipe coupling member includes a coupling body and a sleeve 138 disposed around a cylindrical peripheral wall portion of the coupling body. The sleeve has a locking element receiving hole extending therethrough from an inner peripheral surface to an outer peripheral surface. When the sleeve is in a locking element releasing position where the locking element receiving hole radially aligns with a locking element, the locking element is received in the locking element receiving hole to assume an unlocking position. The locking element receiving hole is configured to block the locking element from passing therethrough radially outward and thus holds the locking element in the unlocking position from outside.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 17, 2019
    Assignee: NITTO KOHKI CO., LTD.
    Inventor: Yuki Imoto
  • Publication number: 20190185986
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Tetsunori MARUYAMA, Yuki IMOTO, Hitomi SATO, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Takashi SHIMAZU
  • Publication number: 20190051754
    Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.
    Type: Application
    Filed: October 12, 2018
    Publication date: February 14, 2019
    Inventors: Junichiro SAKATA, Tetsunori MARUYAMA, Yuki IMOTO
  • Publication number: 20190024835
    Abstract: Provided is a pipe coupling member configured to prevent a coil spring from being plastically deformed or dislodged from a coupling body even when a large force acts on a valve element. A pipe coupling member includes a coupling body having a fluid passage, a valve element displaceable in the fluid passage, and a coil spring urging the valve element toward a closed position. The coil spring is formed by helically winding a wire and has a fitting portion fitted and secured in a spring fitting groove, a locking portion contiguous with the fitting portion and having an outer diameter larger than the inner diameter of the fitting portion when fitted in the spring fitting groove, a valve support portion supporting the valve element, and an expanding-contracting portion extending between the locking portion and the valve support portion to expand and contract. When the coil spring is compressed, the locking portion is supported by the fitting portion and thus prevented from passing through the fitting portion.
    Type: Application
    Filed: September 27, 2018
    Publication date: January 24, 2019
    Inventor: Yuki IMOTO
  • Patent number: 10103272
    Abstract: Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×1020 atoms/cm3 or less is provided.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: October 16, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Tetsunori Maruyama, Yuki Imoto