Abstract: A semiconductor memory device includes a memory pillar; first and second conductive layers on either side of the memory pillar; third and fourth conductive layers and fifth and sixth conductive layer respectively below and above first and second conductive layers; seventh and eighth conductive layers below third and fourth conductive layers; ninth and tenth conductive layers above fifth and sixth conductive layers; memory cells formed between a respective first through tenth conductive layers and the memory pillar; and a control circuit, which applies a read voltage to the first conductive layer, a negative voltage to second, fourth, and sixth conductive layers, and a read pass voltage to other conductive layers, applies the read pass voltage to first, second, fourth, and sixth conductive layers, applies a ground voltage or lower to a first group of conductive layers, and then a ground voltage to a second group of conductive layers.

Abstract: A non-volatile semiconductor memory device includes a first semiconductor layer including a first memory cell transistor including a first channel, a second semiconductor layer including a second memory cell transistor including a second channel, a third semiconductor layer including a third memory cell transistor including a third channel, and a control circuit that controls the first memory cell transistor to the third memory cell transistor so that a write operation can be performed. When performing a write operation on the second memory cell transistor, the control circuit supplies a first voltage that is a reference voltage to the second channel, supplies a second voltage that is greater than the first voltage to the first channel, and then supplies the second voltage to the third channel, thereby boosting the voltage supplied to the first channel to a third voltage that is greater than the second voltage.

Abstract: A semiconductor memory device includes a memory cell array including a first block and a second block, and a control circuit. The control circuit executes a first write operation of writing first data by applying a first voltage to a channel area of a first memory cell transistor of the first block through a bit line and then while the channel area of the first memory cell transistor is in a floating state, applying a program voltage to a first word line. The control circuit starts a second write operation of writing second data into a second memory cell transistor of the second block that is connected to the bit line while the program voltage is applied to the first word line.

Abstract: A memory device includes a memory cell, a word line coupled to the memory cell, a bit line coupled to the memory cell, a first transistor, a first latch, a second transistor, and a third transistor. The first transistor has a gate coupled to a first node coupled to the bit line, and is coupled to a second node. The first latch circuit is coupled to the second node and includes a third node. The second transistor is coupled between the first node and a fourth node A gate of the second transistor coupled to a node different from the third node. The third transistor is coupled between the first node and the fourth node A gate of the third transistor is coupled to the third node.

Abstract: A semiconductor storage device includes a first word line, a second word line, a first select gate line, a second select gate line, a third select gate line, a fourth select gate line, a first memory pillar including a first memory cell connected to the first word line, a first select transistor connected to the first select gate line, a second memory cell connected to the second word line, and a second select transistor connected to the second select gate line, and a logic control circuit configured to perform a read operation to read threshold voltages of the first and second memory cells, respectively. The logic control circuit independently controls the first to fourth select gate lines during the read operation to turn the select transistors electrically connected to memory cells other than the memory cell to be read to off state.

Abstract: A semiconductor memory device capable of reducing the number of executions of sensing is provided. The semiconductor memory device includes memory cells, word lines that are connected to the memory cells, bit lines that are connectable to the memory cells, and sense amplifiers connectable to the bit lines. A writing operation on the memory cell includes a program operation and a verifying operation. In the verifying operation, the sense amplifier executes a first sensing operation against a first voltage level and executes, based on a result of the first sensing operation, either a second sensing operation against a second voltage level that is higher than the first voltage level or a third sensing operation against a third voltage level that is lower than the first voltage level.

Abstract: A semiconductor memory device comprising: circuitry configured to perform control to cause a channel of a first memory string including a first memory cell and a second memory cell connected in series to be in a floating state in which the channel is electrically insulated from a first bit line connected to a first end of the first memory string and a source line connected to a second end of the first memory string while applying a write voltage to a first word line connected to a gate of the first memory cell; and decrease a voltage of a second word line connected to a gate of the second memory cell from a first voltage that is less than the write voltage to a second voltage that is less than the first voltage after placing the channel of the first memory string into the floating state.

Abstract: A memory includes first and second wires. First and second transistors are connected to the first wires and transfer a first and second voltage. Third and fourth transistors are connected to the second wires and transfer the first and second voltages to the second wires. A first memory cell includes a first diode and a first memory element connected in series. The first diode is connected so that a forward bias direction thereof is from the one first wire to the first signal line. A second memory cell includes a second diode and a second memory element connected in series. The second diode is connected so that a forward bias direction thereof is from the second signal line to the one first wire.

Abstract: A semiconductor storage device includes a bit line, a select gate line, a sense amplifier circuit, a first transistor between the bit line and the sense amplifier circuit, and a second transistor between the bit line and a voltage generation circuit. In a first period of a program operation, the first transistor is turned OFF and the second transistor is turned ON, and a voltage of the first bit line is at a first voltage and a voltage of the select gate line is at a second voltage. In a second period of the program operation, the first transistor is turned ON and the second transistor is turned OFF, and a voltage of the first bit line is at a third voltage less than the first voltage and a voltage of the select gate line is at a fourth voltage greater than the second voltage.

Abstract: A semiconductor memory device includes a memory pillar; first and second conductive layers on either side of the memory pillar; third and fourth conductive layers and fifth and sixth conductive layer respectively below and above first and second conductive layers; seventh and eighth conductive layers below third and fourth conductive layers; ninth and tenth conductive layers above fifth and sixth conductive layers; memory cells formed between a respective first through tenth conductive layers and the memory pillar; and a control circuit, which applies a read voltage to the first conductive layer, a negative voltage to second, fourth, and sixth conductive layers, and a read pass voltage to other conductive layers, applies the read pass voltage to first, second, fourth, and sixth conductive layers, applies a ground voltage or lower to a first group of conductive layers, and then a ground voltage to a second group of conductive layers.

Abstract: A semiconductor memory device includes first and second semiconductor pillars, a first string including first memory cells connected in series and a second string including second memory cells connected in series on opposite sides of the first semiconductor pillar, respectively, a third string including third memory cells connected in series and a fourth string including fourth memory cells connected in series, on opposite sides of the second semiconductor pillar, respectively, first word lines, second word lines, and a driver configured to supply different voltages to the first and second word lines during an erasing operation to erase data in the second and fourth memory cells. In the erasing operation, the driver supplies a first voltage higher than a reference voltage to the first word lines, and supplies the reference voltage to the second word lines.

Abstract: A semiconductor device includes a plurality of conductive layers stacked above one another in a first direction and including a first conductive layer, second conductive layers, and third conductive layers, a semiconductor film extending in the first direction through the conductive layers, an insulating film around the semiconductor film between the semiconductor film and the plurality of conductive layers. During a program operation performed on a first memory cell, a program voltage is applied to the first conductive layer while a first voltage is applied to the second conductive layers and a second voltage different from the first voltage is applied to the third conductive layers. The second conductive layers are each connected to gates of second memory cells programmed to store m bits, and the third conductive layers are each connected to gates of third memory cells programmed to store n bits, where n is different from m.

Abstract: The semiconductor memory device of the embodiment includes: a substrate; a first memory pillar extending in a first direction from the substrate, the first memory pillar including first memory cell transistors, a first selection transistor, a second selection transistor, second memory cell transistors, a third selection transistor, a fourth selection transistor, third memory cell transistors, a fifth selection transistor, a sixth selection transistor, fourth memory cell transistors, a seventh selection transistor, and an eighth selection transistor; a first select gate line; first word lines; a second select gate line; a third select gate line; second word lines; a fourth select gate line; a fifth select gate line; third word lines; a sixth select gate line; a seventh select gate line; fourth word lines; and an eighth select gate line.

Abstract: A semiconductor storage device includes a first word line, a second word line, a first select gate line, a second select gate line, a third select gate line, a fourth select gate line, a first memory pillar including a first memory cell connected to the first word line, a first select transistor connected to the first select gate line, a second memory cell connected to the second word line, and a second select transistor connected to the second select gate line, and a logic control circuit configured to perform a read operation to read threshold voltages of the first and second memory cells, respectively. The logic control circuit independently controls the first to fourth select gate lines during the read operation to turn the select transistors electrically connected to memory cells other than the memory cell to be read to off state.

Abstract: A semiconductor storage device includes a bit line, a select gate line, a sense amplifier circuit, a first transistor between the bit line and the sense amplifier circuit, and a second transistor between the bit line and a voltage generation circuit. In a first period of a program operation, the first transistor is turned OFF and the second transistor is turned ON, and a voltage of the first bit line is at a first voltage and a voltage of the select gate line is at a second voltage. In a second period of the program operation, the first transistor is turned ON and the second transistor is turned OFF, and a voltage of the first bit line is at a third voltage less than the first voltage and a voltage of the select gate line is at a fourth voltage greater than the second voltage.

Abstract: A semiconductor device includes a plurality of conductive layers stacked above one another in a first direction and including a first conductive layer, second conductive layers, and third conductive layers, a semiconductor film extending in the first direction through the conductive layers, an insulating film around the semiconductor film between the semiconductor film and the plurality of conductive layers. During a program operation performed on a first memory cell, a program voltage is applied to the first conductive layer while a first voltage is applied to the second conductive layers and a second voltage different from the first voltage is applied to the third conductive layers. The second conductive layers are each connected to gates of second memory cells programmed to store m bits, and the third conductive layers are each connected to gates of third memory cells programmed to store n bits, where n is different from m.

Abstract: The semiconductor memory device of the embodiment includes: a substrate; a first memory pillar extending in a first direction from the substrate, the first memory pillar including first memory cell transistors, a first selection transistor, a second selection transistor, second memory cell transistors, a third selection transistor, a fourth selection transistor, third memory cell transistors, a fifth selection transistor, a sixth selection transistor, fourth memory cell transistors, a seventh selection transistor, and an eighth selection transistor; a first select gate line; first word lines; a second select gate line; a third select gate line; second word lines; a fourth select gate line; a fifth select gate line; third word lines; a sixth select gate line; a seventh select gate line; fourth word lines; and an eighth select gate line.

Abstract: A semiconductor memory device includes a first semiconductor pillar having i first memory cells on a first side and i second memory cells on a second side, a second semiconductor pillar having i third memory cells on a third side and i fourth memory cells on a fourth side, i first word lines (i is an integer of 4 or more) connected to the i first memory cells and the i third memory cells, i second word lines connected to the i second memory cells and the i fourth memory, and a driver. In writing data to the k-th (k is smaller than i and greater than 1) first memory cell, the driver supplies the k-th first word line with a first voltage larger than a reference voltage, and supplies the k-th second word line with a second voltage smaller than the reference voltage.

Abstract: A memory includes first and second wires. First and second transistors are connected to the first wires and transfer a first and second voltage. Third and fourth transistors are connected to the second wires and transfer the first and second voltages to the second wires. A first memory cell includes a first diode and a first memory element connected in series. The first diode is connected so that a forward bias direction thereof is from the one first wire to the first signal line. A second memory cell includes a second diode and a second memory element connected in series. The second diode is connected so that a forward bias direction thereof is from the second signal line to the one first wire.

Abstract: A semiconductor memory device includes a first semiconductor pillar having i first memory cells on a first side and i second memory cells on a second side, a second semiconductor pillar having i third memory cells on a third side and i fourth memory cells on a fourth side, i first word lines (i is an integer of 4 or more) connected to the i first memory cells and the i third memory cells, i second word lines connected to the i second memory cells and the i fourth memory, and a driver. In writing data to the k-th (k is smaller than i and greater than 1) first memory cell, the driver supplies the k-th first word line with a first voltage larger than a reference voltage, and supplies the k-th second word line with a second voltage smaller than the reference voltage.