Patents by Inventor Yuki Kuroda

Yuki Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11073997
    Abstract: Provided is a storage system and a data management method of a storage system enabling system-wide data deduplication. The storage system has a plurality of storage apparatuses in which one or a plurality of logical volumes are provided. Based on data information of data obtained through the generation of a request to write to a logical volume in the storage system, one storage apparatus among the plurality of storage apparatuses calculates, for a plurality of combinations of storage apparatus and logical volume in the storage system, a data capacity when duplicate data is removed for each of the storage apparatuses, calculates the total of the calculated data capacities as the total capacity of the whole storage system, and performs optimal arrangement arithmetic processing to output information indicating a combination with the smallest total capacity among the plurality of combinations.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 27, 2021
    Assignee: HITACHI, LTD.
    Inventors: Yoshio Sonokawa, Yuki Kuroda, Hirokazu Ogasawara, Kozue Fujii
  • Publication number: 20210062907
    Abstract: Disclosed is a gearbox enabling to inhibit defective engagement between a first helical gear and a second helical gear even when a restraint torque is applied. The gearbox includes: the first helical gear; the second helical gear to engage with the first helical gear; a casing including a first member disposed in proximity to the first helical gear and a second member disposed in proximity to the second helical gear; a screw for fastening the first member with the second member, and disposed closer to the first helical gear than an engagement position between the first helical gear and the second helical gear and penetrating at least the second member; and a clip disposed closer to the second helical gear than the engagement position, and formed of a closed curve in such a manner that the first member end and the second member end are enclosed therein.
    Type: Application
    Filed: August 20, 2020
    Publication date: March 4, 2021
    Applicant: TOYOTA BOSHOKU KABUSHIKI KAISHA
    Inventors: Yuki KURODA, Toshiharu KIRIYAMA, Kenji TATEWAKI
  • Publication number: 20200210086
    Abstract: Provided is a storage system and a data management method of a storage system enabling system-wide data deduplication. The storage system has a plurality of storage apparatuses in which one or a plurality of logical volumes are provided. Based on data information of data obtained through the generation of a request to write to a logical volume in the storage system, one storage apparatus among the plurality of storage apparatuses calculates, for a plurality of combinations of storage apparatus and logical volume in the storage system, a data capacity when duplicate data is removed for each of the storage apparatuses, calculates the total of the calculated data capacities as the total capacity of the whole storage system, and performs optimal arrangement arithmetic processing to output information indicating a combination with the smallest total capacity among the plurality of combinations.
    Type: Application
    Filed: September 11, 2019
    Publication date: July 2, 2020
    Inventors: Yoshio SONOKAWA, Yuki KURODA, Hirokazu OGASAWARA, Kozue FUJII
  • Patent number: 9694724
    Abstract: A vehicular seat slide device, includes: a first rail fixed to one of a vehicular floor and a seat; a second rail fixed to the other one of the floor and the seat, and linked to be movable relative to the first rail; a screw rod supported by the second rail to be rotatable around an axial line which extends in a moving direction; a metal case fixed to the first rail, and through which the screw rod is inserted; a resin nut housed in the metal case in a state of being unmovable in the moving direction with respect to the metal case, and screwed to the screw rod; and a metal nut housed in the metal case in a state of not being in contact with the resin nut in the moving direction, and screwed to the screw rod.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: July 4, 2017
    Assignee: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Toshiaki Nagata, Hiroyuki Okazaki, Kenji Tatewaki, Yuki Kuroda
  • Patent number: 9507392
    Abstract: Pieces of working information on workloads, positions of the workloads, pieces of environmental information on cooling facilities, and positions of the cooling facilities are stored as arrangement information. The pieces of working information on the workloads are estimated, and allocation of tentative workloads is deduced for fear the pieces of working information may exceed the performances of a group of information processing devices. Tentative power consumptions and arrangement information resulting from the allocation of the tentative workloads, and tentative power consumptions and arrangement information necessary for the allocation of the tentative workloads are calculated. Tentative cooling powers required to control the cooling facilities are calculated. Allocation of the tentative workloads minimizing the sum total of the tentative power consumptions of the information processing devices and the tentative cooling powers of the cooling facilities is searched.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: November 29, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Tohru Nojiri, Jun Okitsu, Yuki Kuroda, Eiichi Suzuki, Takeshi Kato, Tatsuya Saito
  • Publication number: 20150298581
    Abstract: A vehicular seat slide device, includes: a first rail fixed to one of a vehicular floor and a seat; a second rail fixed to the other one of the floor and the seat, and linked to be movable relative to the first rail; a screw rod supported by the second rail to be rotatable around an axial line which extends in a moving direction; a metal case fixed to the first rail, and through which the screw rod is inserted; a resin nut housed in the metal case in a state of being unmovable in the moving direction with respect to the metal case, and screwed to the screw rod; and a metal nut housed in the metal case in a state of not being in contact with the resin nut in the moving direction, and screwed to the screw rod.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 22, 2015
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Toshiaki NAGATA, Hiroyuki OKAZAKI, Kenji TATEWAKI, Yuki KURODA
  • Patent number: 9104397
    Abstract: It is provided a computer comprising a nonvolatile memory for storing data, a control processor for controlling the saving of data into the nonvolatile memory, and a battery for supplying power to the computer in case of a failure of an external power supply, wherein the control processor checks a charge amount stored in the battery, calculates an amount of data which can be saved in the nonvolatile memory by the battery in case of a failure of the external power supply based on the checked charge amount, and saves data excluding the amount of data that can be saved, out of data which should be saved into the nonvolatile memory, into the nonvolatile memory in advance.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: August 11, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kuroda, Masashi Takada, Yasuyuki Kudo
  • Publication number: 20130111492
    Abstract: Pieces of working information on workloads, positions of the workloads, pieces of environmental information on cooling facilities, and positions of the cooling facilities are stored as arrangement information. The pieces of working information on the workloads are estimated, and allocation of tentative workloads is deduced for fear the pieces of working information may exceed the performances of a group of information processing devices. Tentative power consumptions and arrangement information resulting from the allocation of the tentative workloads, and tentative power consumptions and arrangement information necessary for the allocation of the tentative workloads are calculated. Tentative cooling powers required to control the cooling facilities are calculated. Allocation of the tentative workloads minimizing the sum total of the tentative power consumptions of the information processing devices and the tentative cooling powers of the cooling facilities is searched.
    Type: Application
    Filed: July 13, 2012
    Publication date: May 2, 2013
    Applicant: Hitachi, Ltd.
    Inventors: Tohru Nojiri, Jun Okitsu, Yuki Kuroda, Eiichi Suzuki, Takeshi Kato, Tatsuya Saito
  • Patent number: 7977781
    Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.
    Type: Grant
    Filed: October 30, 2010
    Date of Patent: July 12, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoto Ito, Makoto Saen, Yuki Kuroda
  • Publication number: 20110042825
    Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.
    Type: Application
    Filed: October 30, 2010
    Publication date: February 24, 2011
    Inventors: KIYOTO ITO, Makoto Saen, Yuki Kuroda
  • Patent number: 7834440
    Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: November 16, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoto Ito, Makoto Saen, Yuki Kuroda
  • Publication number: 20100078790
    Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.
    Type: Application
    Filed: May 14, 2009
    Publication date: April 1, 2010
    Inventors: Kiyoto ITO, Makoto Saen, Yuki Kuroda
  • Publication number: 20100078635
    Abstract: As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path.
    Type: Application
    Filed: May 14, 2009
    Publication date: April 1, 2010
    Inventors: Yuki Kuroda, Makoto Saen, Hiroyuki Mizuno, Kiyoto Ito
  • Publication number: 20100005323
    Abstract: A semiconductor integrated circuit with processors incorporated therein, which makes it possible to achieve a good balance between realizing low-power consumption control, and securing a processing performance that the practicability of real time processing is required. The semiconductor integrated circuit with processors incorporated therein is provided with a management unit, combining first control for changing a value of the voltage and a frequency of the clock signal based on control information contained in the program, and second control for changing the voltage value and clock signal frequency according to a progress status of a process by the processor, thereby to accelerate progress of the process by the processor. In a period during which the frequency and voltage of each processor are raised, the power consumption is increased, however it becomes possible to achieve high-speed processing.
    Type: Application
    Filed: June 7, 2006
    Publication date: January 7, 2010
    Inventors: Yuki Kuroda, Hiroshi Tanaka