Abstract: Functional linkers or anchors interconnecting graphene-like carbon, such as nanotubes or graphite sheets, with a conducting material such as a metal, are shown, together with related structures, devices, methods and systems.

Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: A nonvolatile memory device and a data processing system with a reduced layout area are capable of efficiently generating a high voltage without deteriorating the charge transfer efficiency of a charge pump circuit. The charge pump circuit in a nonvolatile memory device includes a plurality of stages of charge pump unit circuits. A voltage generating unit provides, as a control signal to the gate of a first MOS transistor for transferring charges from a first capacitor of a charge pump unit circuit of one stage to a first capacitor at the next stage, a fourth signal having an amplitude of a difference voltage between the power supply voltage and the charge pump voltage of the first capacitor at the one stage. The fourth control signal is obtained from second and third signals each changing in amplitude of the power supply voltage. The second signal is supplied via a second capacitor.

Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: The invention facilitates to meet both of the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic. The controller enables an information storage operation to the nonvolatile memory cells, by means of erase and write processing through boosting of the voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and performs a selection control that selects the application interval of the boosted voltage applied during the information storage operation and so forth. This selection control enables utilizing the nonvolatile memory cells as temporary rewrite areas, and facilitates to meet both of the mode of use that finds precedence in data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.

Abstract: The invention facilitates to meet both of the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic. The controller enables an information storage operation to the nonvolatile memory cells, by means of erase and write processing through boosting of the voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and performs a selection control that selects the application interval of the boosted voltage applied during the information storage operation and so forth. This selection control enables utilizing the nonvolatile memory cells as temporary rewrite areas, and facilitates to meet both of the mode of use that finds precedence in data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.

Abstract: The invention facilitates to meet both of the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic. The controller enables an information storage operation to the nonvolatile memory cells, by means of erase and write processing through boosting of the voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and performs a selection control that selects the application interval of the boosted voltage applied during the information storage operation and so forth. This selection control enables utilizing the nonvolatile memory cells as temporary rewrite areas, and facilitates to meet both of the mode of use that finds precedence in data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.

Abstract: The invention facilitates to meet both of the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic. The controller enables an information storage operation to the nonvolatile memory cells, by means of erase and write processing through boosting of the voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and performs a selection control that selects the application interval of the boosted voltage applied during the information storage operation and so forth. This selection control enables utilizing the nonvolatile memory cells as temporary rewrite areas, and facilitates to meet both of the mode of use that finds precedence in data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.

Abstract: The invention facilitates to meet both of the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic. The controller enables an information storage operation to the nonvolatile memory cells, by means of erase and write processing through boosting of the voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and performs a selection control that selects the application interval of the boosted voltage applied during the information storage operation and so forth. This selection control enables utilizing the nonvolatile memory cells as temporary rewrite areas, and facilitates to meet both of the mode of use that finds precedence in data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.

Abstract: The invention facilitates to meet both of the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic. The controller enables an information storage operation to the nonvolatile memory cells, by means of erase and write processing through boosting of the voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and performs a selection control that selects the application interval of the boosted voltage applied during the information storage operation and so forth. This selection control enables utilizing the nonvolatile memory cells as temporary rewrite areas, and facilitates to meet both of the mode of use that finds precedence in data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.

Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: Disclosed is a nonvolatile memory device and a data processing system with a reduced layout area of a semiconductor chip, capable of efficiently generating a high voltage without deteriorating charge transfer efficiency of a charge pump circuit. In charge pump unit circuits of a plurality of stages provided for a charge pump circuit such as a nonvolatile memory, as a control signal to be supplied to the gate of a first MOS transistor for transferring charges from a first capacitor for charge pump at a stage to a first capacity at the next stage, a fourth signal having an amplitude of a difference voltage between the power supply voltage and the charge pump voltage of the first capacitor at a corresponding stage, obtained from two control signals of a second signal and a third signal each changing in amplitude of the power supply voltage. The second signal is supplied via a second capacitor.