Patents by Inventor Yuki Munetaka
Yuki Munetaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230363148Abstract: An apparatus includes a plurality of memory cells in a memory cell array region; a plurality of word lines extending across the memory cell array region and a peripheral region in which no memory cell is arranged; a plurality of contact plugs on even numbered ones of the plurality of word lines in the peripheral region, respectively; and a plurality of insulating walls on odd numbered ones of the plurality of word lines in the peripheral region, respectively.Type: ApplicationFiled: May 9, 2022Publication date: November 9, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Yuki Munetaka, Tsuyoshi Tomoyama
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Patent number: 11799027Abstract: A semiconductor device includes an active region which is surrounded by a device isolation region on a semiconductor substrate and which extends in a first direction; a silicon pillar which separates the active region along the first direction into a first lower diffusion layer and a second lower diffusion layer; a first gate electrode covering a first side face of the silicon pillar which is located on a side of the first lower diffusion layer; a second gate electrode covering a second side face of the silicon pillar which is located on a side of the second lower diffusion layer; a conductive layer provided on a top face of the silicon pillar; and a device isolation insulating film contacting with a third side face of the silicon pillar which is different from the first side face and the second side face.Type: GrantFiled: August 13, 2020Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Yuki Munetaka, Kazuo Ogawa
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Publication number: 20220302123Abstract: An apparatus includes a semiconductor substrate; a line-shaped trench in the semiconductor substrate, an inner wall of the line-shaped trench being covered with an insulating film; a first conductive member including first and second line-shaped portions, the first line-shaped portion filling a lower portion of the line-shaped trench; and line-shaped second and third conductive members extending along the inner wall of the line-shaped trench and facing each other, the line-shaped second and third conductive members having a void therebetween; wherein the second line-shaped portion of the first conductive member protrudes from a central portion of the first line-shaped portion to fill the void.Type: ApplicationFiled: March 16, 2021Publication date: September 22, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Yuki Munetaka, Toshiyasu Fujimoto
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Publication number: 20200373427Abstract: A semiconductor device includes an active region which is surrounded by a device isolation region on a semiconductor substrate and which extends in a first direction; a silicon pillar which separates the active region along the first direction into a first lower diffusion layer and a second lower diffusion layer; a first gate electrode covering a first side face of the silicon pillar which is located on a side of the first lower diffusion layer; a second gate electrode covering a second side face of the silicon pillar which is located on a side of the second lower diffusion layer; a conductive layer provided on a top face of the silicon pillar; and a device isolation insulating film contacting with a third side face of the silicon pillar which is different from the first side face and the second side face.Type: ApplicationFiled: August 13, 2020Publication date: November 26, 2020Applicant: Micron Technology, Inc.Inventors: Yuki Munetaka, Kazuo Ogawa
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Semiconductor device with silicon pillar having a device isolation film contacting a surface thereof
Patent number: 10804390Abstract: A semiconductor device includes an active region which is surrounded by a device isolation region on a semiconductor substrate and which extends in a first direction; a silicon pillar which separates the active region along the first direction into a first lower diffusion layer and a second lower diffusion layer; a first gate electrode covering a first side face of the silicon pillar which is located on a side of the first lower diffusion layer; a second gate electrode covering a second side face of the silicon pillar which is located on a side of the second lower diffusion layer; a conductive layer provided on a top face of the silicon pillar; and a device isolation insulating film contacting with a third side face of the silicon pillar which is different from the first side face and the second side face.Type: GrantFiled: August 19, 2014Date of Patent: October 13, 2020Assignee: Micron Technology, Inc.Inventors: Yuki Munetaka, Kazuo Ogawa -
Publication number: 20150069502Abstract: A semiconductor device includes an active region which is surrounded by a device isolation region on a semiconductor substrate and which extends in a first direction; a silicon pillar which separates the active region along the first direction into a first lower diffusion layer and a second lower diffusion layer; a first gate electrode covering a first side face of the silicon pillar which is located on a side of the first lower diffusion layer; a second gate electrode covering a second side face of the silicon pillar which is located on a side of the second lower diffusion layer; a conductive layer provided on a top face of the silicon pillar; and a device isolation insulating film contacting with a third side face of the silicon pillar which is different from the first side face and the second side face.Type: ApplicationFiled: August 19, 2014Publication date: March 12, 2015Inventors: Yuki MUNETAKA, Kazuo OGAWA
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Patent number: 8357577Abstract: A manufacturing method of a semiconductor device includes the steps of: forming an insulating pillar on the main surface of a silicon substrate; forming a protective film on the side surface of the insulating pillar; forming a silicon pillar on the main surface of the silicon substrate; forming a gate insulating film on the side surface of the silicon pillar; and forming first and second gate electrodes so as to contact each other and so as to cover the side surfaces of the silicon pillar and insulating pillar, respectively. According to the present manufacturing method, the protective film is formed on the side surface of the insulating pillar as a dummy pillar, thus preventing the dummy pillar from being eroded when the silicon pillar for channel is processed into a transistor. Therefore, it is possible to reduce a probability of occurrence of gate electrode disconnection.Type: GrantFiled: October 5, 2011Date of Patent: January 22, 2013Assignee: Elpida Memory, Inc.Inventors: Yuki Munetaka, Yoshihiro Takaishi
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Publication number: 20120100682Abstract: A manufacturing method of a semiconductor device includes the steps of: forming an insulating pillar on the main surface of a silicon substrate; forming a protective film on the side surface of the insulating pillar; forming a silicon pillar on the main surface of the silicon substrate; forming a gate insulating film on the side surface of the silicon pillar; and forming first and second gate electrodes so as to contact each other and so as to cover the side surfaces of the silicon pillar and insulating pillar, respectively. According to the present manufacturing method, the protective film is formed on the side surface of the insulating pillar as a dummy pillar, thus preventing the dummy pillar from being eroded when the silicon pillar for channel is processed into a transistor. Therefore, it is possible to reduce a probability of occurrence of gate electrode disconnection.Type: ApplicationFiled: October 5, 2011Publication date: April 26, 2012Applicant: Elpida Memory, Inc.Inventors: Yuki Munetaka, Yoshihiro Takaishi