Patents by Inventor Yuki Okamoto
Yuki Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12132334Abstract: A semiconductor device with reduced power consumption is provided. The semiconductor device includes a node ND1, a node ND2, a resistor, a capacitor, and a comparison circuit. The resistor is electrically connected in series between one of a positive electrode and a negative electrode of a secondary battery and a first terminal. The resistor has a function of converting current flowing between the one of the positive electrode and the negative electrode of the secondary battery and the first terminal into a first voltage. The first voltage is added to a voltage of the node ND2 through the capacitor. The comparison circuit has a function of comparing a voltage of the node ND1 and the voltage of the node ND2. The comparison circuit outputs a signal that notifies detection of overcurrent when the voltage of the node ND2 is higher than the voltage of the node ND1.Type: GrantFiled: November 12, 2019Date of Patent: October 29, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kei Takahashi, Yuki Okamoto, Minato Ito, Takahiko Ishizu, Hiroki Inoue, Shunpei Yamazaki
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Publication number: 20240339809Abstract: A semiconductor laser module includes: a heat sink; a first electrode disposed in a first region of the heat sink; an insulating layer disposed on the first electrode; a submount disposed in a second region of the heat sink, the second region being different from the first region, the submount being electrically and thermally conductive; a laser diode element disposed on the submount, the laser diode element emitting a laser beam; a feed structure disposed on the laser diode element, the feed structure being electrically and thermally conductive; and a second electrode provided on the insulating layer and the feed structure such that the second electrode is in contact with the insulating layer and the feed structure. A positional relationship between the heat sink, the first electrode, the insulating layer, and the second electrode is fixed by an adhesive.Type: ApplicationFiled: August 29, 2022Publication date: October 10, 2024Applicant: Mitsubishi Electric CorporationInventors: Yuki OKAMOTO, Daisuke MORITA
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Publication number: 20240331630Abstract: A novel electronic device is provided. The electronic device includes a display apparatus, an arithmetic portion, and a gaze detection portion, and the display apparatus includes a functional circuit and a display portion divided into a plurality of sub-display portions. The gaze detection portion has a function of detecting a user's gaze. The arithmetic portion has a function of dividing the plurality of sub-display portions between a first section and a second section using a detection result of the gaze detection portion. The first section includes a region overlapping with a user's gaze point. The functional circuit has a function of making a driving frequency of the second section lower than a driving frequency of the first section.Type: ApplicationFiled: June 30, 2022Publication date: October 3, 2024Inventors: Munehiro KOZUMA, Tatsuya ONUKI, Hidetomo KOBAYASHI, Takanori MATSUZAKI, Yuki OKAMOTO, Minato ITO, Yusuke KOUMURA, Yoshiyuki KUROKAWA, Hisao IKEDA, Hiromichi GODO
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Publication number: 20240332262Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate.Type: ApplicationFiled: June 12, 2024Publication date: October 3, 2024Inventors: Tatsuya ONUKI, Takanori MATSUZAKI, Yuki OKAMOTO, Shunpei YAMAZAKI
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Publication number: 20240322313Abstract: A power storage cell includes a cathode, an anode, a separator, and a sealing portion. The sealing portion includes a first resin layer, a second resin layer, a third resin layer provided between the first resin layer and the second resin layer and welded to the first resin layer and the second resin layer, and a welded area formed by an outer edge portion of the first resin layer, an outer edge portion of the second resin layer, and an outer edge portion of the third resin layer being integrated with each other by welding. An inner edge of the welded area is positioned outward of an inner edge of a bonded area between the first resin layer and the current collector and an inner edge of a bonded area between the second resin layer and the current collector.Type: ApplicationFiled: January 12, 2022Publication date: September 26, 2024Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Yuki OKAMOTO, Ryota KAMIYA
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Publication number: 20240321205Abstract: The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element.Type: ApplicationFiled: June 23, 2022Publication date: September 26, 2024Inventors: Yuki OKAMOTO, Tatsuya ONUKI, Hidetomo KOBAYASHI, Munehiro KOZUMA, Takanori MATSUZAKI, Susumu KAWASHIMA, Yutaka OKAZAKI
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Patent number: 12098670Abstract: This diesel engine comprises: an engine body part in which a cylinder head is fastened to an upper section of a cylinder block; a turbocharger; and an exhaust gas post-treatment device. A cooling fan is provided on the front side in the front-rear direction of the engine body part. The cylinder head is configured to have an exhaust side on the left side in the engine width direction, and an intake side on the right side. The exhaust gas post-treatment device is disposed above the cylinder head so as to extend in the engine front-rear direction. The turbocharger is disposed on the exhaust side of the cylinder head and is configured to spray compressed air in the engine front-rear direction.Type: GrantFiled: August 25, 2021Date of Patent: September 24, 2024Assignee: YANMAR HOLDINGS CO., LTD.Inventors: Yuki Okamoto, Masataka Uchibori
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Publication number: 20240311690Abstract: A data generation device configured to generate data in machine learning for making a determination on an object includes an original data displaying unit configured to display, on a displaying unit, first original data on which data augmentation is to be performed, the first original data including the object; a parameter receiver configured to receive an input of a parameter related to the data augmentation; a generated data displaying unit configured to display, on the displaying unit, generated data generated by the data augmentation for something other than the object in the first original data on the basis of the parameter; and an adoptability receiver configured to receive whether or not to adopt the data augmentation based on the parameter. With the above configuration, it is possible to determine the parameter to be finally adopted while confirming the result of data generation based on the parameter designated by the user.Type: ApplicationFiled: February 25, 2022Publication date: September 19, 2024Inventors: Yuki Hirohashi, Seitaro Mura, Mami Miyamoto, Atsushi Hashimoto, Takahiro Toku, Naoki Tsuchiya, Yoshihisa Ijiri, Yamato Okamoto
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Publication number: 20240300474Abstract: The present disclosure provides a hybrid vehicle control system for controlling a vehicle having a motor and an engine. The system executes the following processes. The first process is determining whether a situation which the vehicle is currently facing is a situation in which high accuracy is required for control of driving of the vehicle or not. The second process is selecting only an EV mode under a situation in which high accuracy is required for the control. The third process is selecting an engine activation mode only under a situation in which high accuracy is not required for the control. The EV mode is a mode in which the engine is stopped and the vehicle is driven by the motor. The engine activation mode is a mode in which the engine is activated for at least one of power generation for charging a battery and driving the vehicle.Type: ApplicationFiled: March 7, 2024Publication date: September 12, 2024Inventors: Hiroya CHIBA, Takehiko HANADA, Tatsuya SUGANO, Noriyuki TSURUOKA, Ryuji OKAMURA, Amane YAJIMA, Yuki OKAMOTO
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Publication number: 20240305060Abstract: A semiconductor laser module includes: a manifold having a water passage through which cooling water can flow, the water passage being provided inside the manifold; a heat sink disposed on the manifold; a first electrode disposed in a first region of the heat sink; an insulating layer disposed on the first electrode; a submount disposed in a second region of the heat sink, a laser diode element disposed on the submount, the laser diode element emitting a laser beam; a feed structure disposed on the laser diode element; and a second electrode provided on the insulating layer and the feed structure such that the second electrode is in contact with the insulating layer and the feed structure. The water passage has a curved portion in the manifold, the curved portion including a continuous curved surface with no corner portion.Type: ApplicationFiled: August 29, 2022Publication date: September 12, 2024Applicant: Mitsubishi Electric CorporationInventors: Yuki OKAMOTO, Daisuke MORITA
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Patent number: 12086954Abstract: A display apparatus that can display a high-resolution image can be provided. In the display apparatus, a first layer and a second layer are stacked. In the first layer, an arithmetic circuit and a data driver circuit and are provided, and in the second layer, a display portion is provided. In the arithmetic circuit, a neural network is configured. The display portion has a region overlapping with the data driver circuit. The arithmetic circuit has a function of performing arithmetic processing using the neural network on image data and supplying the arithmetically-processed image data to the data driver circuit.Type: GrantFiled: October 19, 2020Date of Patent: September 10, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuki Okamoto, Tatsuya Onuki
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Patent number: 12080377Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.Type: GrantFiled: March 4, 2021Date of Patent: September 3, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuki Okamoto, Tatsuya Onuki, Munehiro Kozuma, Takanori Matsuzaki
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Publication number: 20240285547Abstract: In one embodiment, the object of the present invention is to provide a nephrotoxicity reducing agent for a pharmaceutical composition comprising an antisense oligomer, and a method for reducing nephrotoxicity of the pharmaceutical composition. In one embodiment, the present invention relates to a nephrotoxicity reducing agent for a pharmaceutical composition comprising an antisense oligomer, wherein the nephrotoxicity reducing agent comprises a sugar alcohol and is used in an amount such that the concentration of the sugar alcohol in the pharmaceutical composition is 1 mg/ml to 400 mg/mL.Type: ApplicationFiled: July 8, 2022Publication date: August 29, 2024Applicants: Nippon Shinyaku Co., Ltd., National University Corporation Kobe UniversityInventors: Satoru SONOKE, Kae FUJIWARA, Youhei SATOU, Tatsushi WAKAYAMA, Hirofumi MASUDA, Ryosuke SEKI, Takuma MATSUBARA, Yuki NUMAKURA, Kentaro OKAMOTO, Tatsushi TODA, Mariko IKEDA, Kazuhiro KOBAYASHI
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Publication number: 20240285770Abstract: In one embodiment, the object of the present invention is to provide a precipitation suppressing agent for an antisense oligomer in urine of a subject to whom a pharmaceutical composition comprising an antisense oligomer has been administered, and a method for suppressing precipitation of an antisense oligomer in urine, in a subject to whom the pharmaceutical composition has been administered. In one embodiment, the present invention relates to a precipitation suppressing agent for an antisense oligomer in urine of a subject to whom a pharmaceutical composition comprising an antisense oligomer has been administered, wherein the precipitation suppressing agent comprises a sugar other than glucose and is used in an amount such that the concentration of the sugar in the pharmaceutical composition is 0.5 mg/mL to 3000 mg/mL.Type: ApplicationFiled: July 8, 2022Publication date: August 29, 2024Applicant: Nippon Shinyaku Co., Ltd.Inventors: Yukiko ENYA, Yuki NUMAKURA, Kentaro OKAMOTO, Kazuki AGATA
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Patent number: 12074179Abstract: An imaging device with an arithmetic function in which the circuit size is reduced is provided. The imaging device includes a plurality of pixel blocks. Each of the pixel blocks includes N (N is an integer greater than or equal to 1) first circuits, N second circuits, and a third circuit. Each of the first circuits includes a photoelectric conversion device, and the photoelectric conversion device has a function of converting incident light into an electrical signal and has a function of outputting a first signal that is obtained by binarizing the electrical signal to the second circuit. Each of the second circuits has a function of outputting a second signal that is obtained by multiplying the first signal by a weight coefficient to a third circuit. When the N second signals are output to a wiring electrically connected to the third circuit, addition is performed. The first circuit includes a transistor, and an OS transistor is preferably used as the transistor.Type: GrantFiled: December 14, 2020Date of Patent: August 27, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Seiichi Yoneda, Toshiki Hamada, Yuki Okamoto, Shunpei Yamazaki
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Publication number: 20240268096Abstract: A memory device capable of reading multi-bit data at a time is provided. The memory device includes a first layer and a second layer positioned above or below the first layer. The first layer includes a first transistor and a first capacitor, and the second layer includes a second transistor and a second capacitor. Each of the first and second capacitors is a trench capacitor, and the trench length of the second capacitor is larger than the trench length of the first capacitor. A voltage retained in the first capacitor corresponds to a lower bit signal of data, and a voltage retained in the second capacitor corresponds to a higher bit signal of the data.Type: ApplicationFiled: January 26, 2024Publication date: August 8, 2024Inventors: Yuki OKAMOTO, Takanori MATSUZAKI, Hiroki INOUE
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Publication number: 20240255288Abstract: An automated valet parking management device according to the present disclosure includes one or more processors and one or more memory devices. The one or more memory devices store map information on a parking facility including a loading dock and positional information on a door of a cargo room included in a cargo vehicle that performs at least one of a carry-in and a carry-out of a cargo in the loading dock. The one or more processors execute parking arrangement processing for determining a parking position and a parking direction of the cargo vehicle when the cargo working operation of the cargo vehicle is performed based on the map information and the positional information on the door before the cargo working operation is started by the cargo vehicle.Type: ApplicationFiled: December 7, 2023Publication date: August 1, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroya CHIBA, Tatsuya SUGANO, Yuhei OKA, Yuki OKAMOTO
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Publication number: 20240250097Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.Type: ApplicationFiled: February 12, 2024Publication date: July 25, 2024Inventors: Yuki OKAMOTO, Yoshiyuki KUROKAWA, Hiroki INOUE, Takuro OHMARU
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Publication number: 20240251567Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a first substrate, a first element layer provided in contact with a second substrate, and a first through electrode provided in the second substrate and the first element layer. The first element layer includes a first memory cell, a first electrode, a second electrode, and a third electrode. The first memory cell includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The first electrode is electrically connected to the third electrode via the second electrode. The third electrode is provided to be exposed on a surface of the first element layer. The first through electrode is provided to be exposed on a surface of the second substrate and is electrically connected to the first electrode.Type: ApplicationFiled: May 19, 2022Publication date: July 25, 2024Inventors: Takanori MATSUZAKI, Tatsuya ONUKI, Yuki OKAMOTO
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Patent number: 12034322Abstract: A battery control circuit having a novel structure, a battery protection circuit having a novel structure, and a power storage device including the battery circuit are provided. A semiconductor device includes n cell balancing circuits that respectively correspond to one secondary battery and each include a transistor, a comparator circuit, and a capacitor. In each of the n cell balancing circuits, an inverting input terminal of the comparator circuit and one electrode of the capacitor are electrically connected to one of a source and a drain of the transistor.Type: GrantFiled: January 14, 2020Date of Patent: July 9, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuki Okamoto, Takahiko Ishizu, Kei Takahashi, Takayuki Ikeda