Patents by Inventor Yuki Okamoto

Yuki Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143100
    Abstract: A display device with excellent visibility can be provided. The display device includes a display region displayed by a light-emitting element. In the display region, a point touched by a user is a first point, a point which has been touched by the user prior to the first point is a second point, a vector that starts at the first point and ends at the second point is a first vector, a vector obtained by multiplying the first vector by k (k is a real number) is a second vector, and a point that is the second vector away from the first point is a third point, the display region includes a first region and a second region obtained by excluding the first region from the display region, The first region includes a first circle and a second circle, the center of the first circle is the first point, and the center of the second circle is the third point. The luminance in the first region is higher than the luminance in the second region.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 2, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Yuki Okamoto, Kei Takahashi, Shunpei Yamazaki
  • Publication number: 20240147708
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first substrate provided with a first peripheral circuit having a function of driving a first memory cell and a first memory cell layer including a second substrate and a first element layer including the first memory cell. The first memory cell includes a first transistor and a first capacitor. The first transistor includes a semiconductor layer including a metal oxide in its channel formation region. The first memory cell layer is provided to be stacked over the first substrate in a direction perpendicular or substantially perpendicular to a surface of the first substrate. The second substrate includes a circuit for performing writing of data to or reading of data from the first memory cell. The first peripheral circuit and the first memory cell are electrically connected to each other through a first through electrode provided in the second substrate and the first element layer.
    Type: Application
    Filed: April 26, 2022
    Publication date: May 2, 2024
    Inventors: Takanori MATSUZAKI, Yuki OKAMOTO, Tatsuya ONUKI, Hitoshi KUNITAKE
  • Publication number: 20240139883
    Abstract: Provided is a practical method for processing a gallium oxide substrate that enables the gallium oxide substrate to be cut vertically and horizontally in a lattice shape. Mechanical scribing processing in which a cut groove is engraved on a main plane by a scribing tool along a planned cutting line parallel to an X direction, which is defined as a direction parallel to an intersection line between the main plane and a plane (100), is performed using a gallium oxide substrate of which the main plane is the plane (001), laser scribing processing to be altered by scanning with a laser beam along a planned cutting line parallel to the Y direction is performed, and cutting is performed by break along planned cutting lines in the X direction and the Y direction after the mechanical scribing processing and after the laser scribing processing.
    Type: Application
    Filed: December 6, 2021
    Publication date: May 2, 2024
    Applicant: MITSUBISHI DIAMOND INDUSTRIAL CO., LTD.
    Inventors: Mitsuru KITAICHI, Yoshiyuki ASAI, Hirokazu OKAMOTO, Yuki TSUJIMOTO
  • Publication number: 20240144421
    Abstract: A display apparatus that can display a high-resolution image can be provided. In the display apparatus, a first layer and a second layer are stacked. In the first layer, an arithmetic circuit and a data driver circuit and are provided, and in the second layer, a display portion is provided. In the arithmetic circuit, a neural network is configured. The display portion has a region overlapping with the data driver circuit. The arithmetic circuit has a function of performing arithmetic processing using the neural network on image data and supplying the arithmetically-processed image data to the data driver circuit.
    Type: Application
    Filed: October 19, 2020
    Publication date: May 2, 2024
    Inventors: Yuki OKAMOTO, Tatsuya ONUKI
  • Publication number: 20240147687
    Abstract: A memory device that can be highly integrated is provided. The memory device includes a first transistor and a second transistor in a memory cell, and small-area vertical transistors each including a channel formation region on a side surface of an opening portion provided in an insulating layer are used as the two transistors. The memory cell includes a conductor having a function of a gate electrode of the first transistor and a function of one of a source electrode and a drain electrode of the second transistor. The memory cells are placed in a staggered arrangement, so that the memory device can be highly integrated.
    Type: Application
    Filed: October 20, 2023
    Publication date: May 2, 2024
    Inventors: Takanori MATSUZAKI, Hiroki INOUE, Yuki OKAMOTO
  • Patent number: 11973198
    Abstract: A semiconductor device capable of detecting a micro-short circuit of a secondary battery is provided. The semiconductor device includes a first source follower, a second source follower, a transistor, a capacitor, and a comparator. A negative electrode potential and a positive electrode potential of the secondary battery are supplied to the semiconductor device, a first potential is input to the first source follower, and a second potential is input to the second source follower. A signal for controlling the conduction state of the transistor is input to a gate of the transistor, and an output potential of the first source follower related to the potential between the positive electrode and the negative electrode of the secondary battery is sampled.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: April 30, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takanori Matsuzaki, Kei Takahashi, Takahiko Ishizu, Yuki Okamoto, Minato Ito
  • Publication number: 20240135246
    Abstract: A data generation method for generating data for domain generalization in machine learning includes performing, with a computer, augmentation using training data as raw data usable to train a machine learning model, and extracting, with the computer, a dataset including the raw data and data generated through the augmentation as a dataset for the domain generalization.
    Type: Application
    Filed: January 18, 2022
    Publication date: April 25, 2024
    Inventors: Mami Miyamoto, Seitaro Mura, Yuki Hirohashi, Atsushi Hashimoto, Takahiro Toku, Naoki Tsuchiya, Yoshihisa Ijiri, Yamato Okamoto
  • Publication number: 20240128711
    Abstract: A semiconductor laser module includes a laser emission unit including a laser diode element that emits a laser beam, and a first electrode and a second electrode that supply current to the laser diode element; a base member that supports and fixes the laser emission unit; a fast-axis collimator that collimates a fast-axis direction component of the laser beam emitted from the laser diode element; and a slow-axis collimator that collimates a slow-axis direction component of the laser beam emitted from the laser diode element. The base member protrudes in a direction of emission of the laser beam with respect to the laser emission unit. The fast-axis collimator is fixed to the laser emission unit in an optical path of the laser emission unit where the laser beam is emitted. The slow-axis collimator is fixed to the base member in the optical path of the laser beam.
    Type: Application
    Filed: April 4, 2022
    Publication date: April 18, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuki OKAMOTO, Daisuke MORITA
  • Publication number: 20240120627
    Abstract: A power storage device comprises: an electrode stack comprising a plurality of bipolar electrodes and a pair of outermost current collectors; an inner voltage detection terminal; a housing; and a pair of outer voltage detection terminals. Each of the plurality of bipolar electrodes has a current collector, a positive electrode active material layer, and a negative electrode active material layer. The inner voltage detection terminal is electrically connected to the current collector. Each of the pair of outer voltage detection terminals is thicker than the inner voltage detection terminal. The housing is located between the pair of outer voltage detection terminals in the stacking direction. A dimension of the housing in the stacking direction is equal to or less than a distance between the pair of outer voltage detection terminals in the stacking direction.
    Type: Application
    Filed: August 28, 2023
    Publication date: April 11, 2024
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroyuki NAKAYAMA, Yuki OKAMOTO, Fumihiko ISHIGURO, Takayuki HIROSE
  • Patent number: 11940215
    Abstract: Disclosed is a blast furnace apparatus includes: a rotating chute; a profile measurement device configured to measure surface profiles of a burden charged into the furnace; and a tilt angle controller configured to control a tilt angle of the chute, in which the device includes a radio wave distance meter installed on the furnace top and configured to measure the distance to the surface of the burden, derives the profiles on a basis of distance data for the entire furnace obtained by scanning a detection wave of the distance meter in the furnace in a circumferential direction, and includes at least one of arithmetic units configured to command during rotation, on a basis of the surface profiles obtained, the controller to change the tilt angle of the chute, or a controller to change a rotational speed of the chute or a feed speed of the burden fed to the chute.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: March 26, 2024
    Assignee: JFE STEEL CORPORATION
    Inventors: Yusuke Kashihara, Yuki Okamoto, Natsuo Ishiwata
  • Publication number: 20240088620
    Abstract: A semiconductor laser module includes a heat sink, a first electrode disposed in a first region of the heat sink, an electrically insulating layer disposed on the first electrode, a submount that is disposed in a second region of the heat sink and is electrically conductive and thermally conductive, a laser diode element that is disposed on the submount and emits a laser beam, a feed structure that is disposed on the laser diode element and is electrically conductive, thermally conductive, and elastic, and a second electrode disposed on and in contact with the electrically insulating layer and the feed structure. The second electrode includes an electrode-facing portion having a flat surface in contact with the electrically insulating layer, and a protruding portion having a flat surface in contact with the feed structure, and protruding toward the heat sink with respect to the electrode-facing portion.
    Type: Application
    Filed: April 4, 2022
    Publication date: March 14, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuki OKAMOTO, Daisuke MORITA
  • Patent number: 11908876
    Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: February 20, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Okamoto, Yoshiyuki Kurokawa, Hiroki Inoue, Takuro Ohmaru
  • Publication number: 20240055665
    Abstract: A power storage device includes a first electrode including a first active material layer formed on a first surface, a second electrode including a second active material layer formed on a first surface, a separator, and a spacer. The first active material layer has a longitudinal side of a first length. The second area has a second length between the spacer and the first active material layer. A ratio of the second length to the first length is 0.02 or less. At least one of corners of the first active material layer has a shape chamfered in an arc shape. A radius of curvature at a portion of the corner having a maximum curvature is 5 mm or more.
    Type: Application
    Filed: October 14, 2021
    Publication date: February 15, 2024
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Yuki OKAMOTO, Yoshikatsu KAWABATA, Masaki INOUE
  • Publication number: 20240029774
    Abstract: In a memory cell including a ferroelectric capacitor, data is read without data destruction. When the reading operation is performed in the memory cell including the ferroelectric capacitor, voltage applied to the counter electrode of the ferroelectric capacitor is gradually increased so as not to cause polarization destruction in the ferroelectric capacitor. A first reading operation from the memory cell is performed by applying a first voltage that does not cause polarization inversion of the ferroelectric layer to the capacitor, a second reading operation from the memory cell is performed by applying a second voltage that does not cause polarization inversion of the ferroelectric layer to the capacitor, and the second voltage is higher than the first voltage.
    Type: Application
    Filed: October 8, 2021
    Publication date: January 25, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Okamoto, Tatsuya ONUKI, Kazuma FURUTANI
  • Publication number: 20240029773
    Abstract: A semiconductor device with high reliability is provided. The semiconductor device includes a memory cell including a first ferroelectric capacitor and a reference memory cell including a second ferroelectric capacitor. In a first period, first binary data is written to the memory cell, and first reference binary data is written to the reference memory cell. In a second period, the first binary data is read from the memory cell, and the first reference binary data is read from the reference memory cell. In a third period, logic operation of the first binary data and the first reference binary data is performed. In a fourth period, second binary data is written to the memory cell, and second reference binary data is written to the reference memory cell. A value of the first binary data and a value of the second binary data are different from each other, and a value of the first reference binary data and a value of the second reference binary data are different from each other.
    Type: Application
    Filed: September 9, 2021
    Publication date: January 25, 2024
    Inventors: Yuki OKAMOTO, Tatsuya ONUKI, Takanori MATSUZAKI
  • Publication number: 20240021933
    Abstract: A power storage module includes: a stack including power storage cells stacked in a first direction and having stack side surfaces that extends in the first direction; and a sealing member formed in contact with the stack side surfaces. The power storage cells each includes: a first electrode including a first electrode plate having a first surface and a first active material layer formed on the first surface; a second electrode including a second electrode plate having a second surface and a second active material layer having an electrode polarity different from that of the first active material layer and formed on the second surface; and a spacer. A portion of the sealing member disposed on at least one of the stack side surfaces serves as a low elastic modulus portion that has an elastic modulus lower than that of the spacer.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 18, 2024
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Yuki OKAMOTO, Osamu OHMORI, Kayo MIZUNO, Mutsumi TAKAHASHI, Kanae MURASE
  • Patent number: 11874981
    Abstract: A display device with excellent visibility can be provided. The display device includes a display region displayed by a light-emitting element. In the display region, a point touched by a user is a first point, a point which has been touched by the user prior to the first point is a second point, a vector that starts at the first point and ends at the second point is a first vector, a vector obtained by multiplying the first vector by k (k is a real number) is a second vector, and a point that is the second vector away from the first point is a third point, the display region includes a first region and a second region obtained by excluding the first region from the display region. The first region includes a first circle and a second circle, the center of the first circle is the first point, and the center of the second circle is the third point. The luminance in the first region is higher than the luminance in the second region.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: January 16, 2024
    Inventors: Takayuki Ikeda, Yuki Okamoto, Kei Takahashi, Shunpei Yamazaki
  • Patent number: 11870393
    Abstract: An oscillator capable of quick startup is provided. A transistor is provided between an output terminal of a certain stage inverter and an input terminal of the following stage inverter included in the voltage controlled oscillator. With the use of the on resistance of the transistor, the oscillation frequency of the clock signal is controlled. While supply of the power supply voltage is stopped, a signal that is input to the input terminal of the inverter just before supply of the power supply voltage is stopped is stored by turning off the transistor. This operation makes it possible to immediately output a clock signal that has the same frequency as that before supply of the power supply voltage is stopped at the time when the power supply voltage is supplied again.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Okamoto, Yoshiyuki Kurokawa
  • Patent number: 11867503
    Abstract: An anomaly detection system that outputs an anomaly detection signal before a safety valve of a secondary battery is opened is provided. The anomaly detection system includes a strain sensor, a memory, and a comparator. The memory has a function of retaining an analog potential, and the comparator has a function of comparing a potential output by the strain sensor and the analog potential retained by the memory. The strain sensor is attached to the secondary battery before use, and a predetermined potential is retained in the memory. When a housing of the secondary battery expands while the secondary battery is used, and the potential output by the strain sensor becomes higher (or lower) than the predetermined potential, an anomaly detection signal is output.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Ryota Tajima, Yuki Okamoto, Shunpei Yamazaki
  • Patent number: 11823733
    Abstract: A memory device includes m memory cell blocks, m×(k+1) word lines, n bit lines, and a word line driver circuit (m, k, and n are each an integer greater than or equal to 1). The memory cell block includes memory cells of (k+1) rows×n columns, and each of the memory cells is electrically connected to a word line and a bit line. The word line driver circuit has a function of outputting signals to m×k word lines that are selected from m×(k+1) word lines by using a switch transistor, and selection information is written to a gate of the switch transistor by using a transistor having a low off-state current. The memory cells of k rows×n columns included in the memory cell block are normal memory cells, and each of the memory cell blocks includes redundant memory cells of one row×n columns.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 21, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hitoshi Kunitake, Yuto Yakubo, Takanori Matsuzaki, Yuki Okamoto, Tatsuya Onuki