Patents by Inventor Yuki Okukawa
Yuki Okukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8537598Abstract: A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage.Type: GrantFiled: May 18, 2012Date of Patent: September 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Maejima, Yuki Okukawa
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Publication number: 20120230082Abstract: A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage.Type: ApplicationFiled: May 18, 2012Publication date: September 13, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi MAEJIMA, Yuki Okukawa
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Patent number: 8207613Abstract: A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring.Type: GrantFiled: March 5, 2010Date of Patent: June 26, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuki Okukawa, Satoru Takase
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Patent number: 8199557Abstract: A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage.Type: GrantFiled: March 8, 2010Date of Patent: June 12, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Maejima, Yuki Okukawa
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Patent number: 8195993Abstract: A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.Type: GrantFiled: July 8, 2011Date of Patent: June 5, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuki Okukawa, Kazushige Kanda
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Publication number: 20110264969Abstract: A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.Type: ApplicationFiled: July 8, 2011Publication date: October 27, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yuki OKUKAWA, Kazushige Kanda
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Patent number: 8006145Abstract: A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.Type: GrantFiled: March 31, 2009Date of Patent: August 23, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuki Okukawa, Kazushige Kanda
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Publication number: 20100237512Abstract: A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring.Type: ApplicationFiled: March 5, 2010Publication date: September 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuki OKUKAWA, Satoru TAKASE
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Publication number: 20100232207Abstract: A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage.Type: ApplicationFiled: March 8, 2010Publication date: September 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi MAEJIMA, Yuki Okukawa
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Publication number: 20090265591Abstract: A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.Type: ApplicationFiled: March 31, 2009Publication date: October 22, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Yuki Okukawa, Kazushige Kanda