Patents by Inventor Yuki SEKINO

Yuki SEKINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9825100
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of conducting layers, a semiconductor layer, a variable resistive element, and a first wiring. The plurality of conducting layers are laminated in a first direction at predetermined pitches. The conducting layers extend in a second direction. The second direction is along the surface of the substrate. The semiconductor layer extends in the first direction. The variable resistive element is disposed at an intersection point between the plurality of conducting layers and the semiconductor layer. The first wiring is opposed to an inside of the semiconductor layer via a gate insulating film. The first wiring extends in the first direction. The semiconductor layer at least includes a first part and a second part. The first part is upward of the conducting layer on a lowermost layer. The second part is downward of the first part. The first part has a first length in a third direction.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: November 21, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuki Sekino, Takashi Izumida, Nobutoshi Aoki
  • Publication number: 20170069635
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a semiconductor body of a first conductivity type, a memory film, and a first semiconductor layer of the first conductivity type. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body includes a first portion, a second portion, and a third portion. The second portion is provided between the first portion and the third portion. The memory film is provided between the semiconductor body and at least a part of the electrode layers. A concentration of a first conductivity type carrier of the first semiconductor layer is higher than a concentration of the first conductivity type carrier of the third portion. The second portion includes a channel of a selection transistor. The third portion includes a channel of a memory cell.
    Type: Application
    Filed: March 10, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hikari TAJIMA, Yuki Sekino, Masaki Kondo
  • Publication number: 20170062523
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of conducting layers, a semiconductor layer, a variable resistive element, and a first wiring. The plurality of conducting layers are laminated in a first direction at predetermined pitches. The conducting layers extend in a second direction. The second direction is along the surface of the substrate. The semiconductor layer extends in the first direction. The variable resistive element is disposed at an intersection point between the plurality of conducting layers and the semiconductor layer. The first wiring is opposed to an inside of the semiconductor layer via a gate insulating film. The first wiring extends in the first direction. The semiconductor layer at least includes a first part and a second part. The first part is upward of the conducting layer on a lowermost layer. The second part is downward of the first part. The first part has a first length in a third direction.
    Type: Application
    Filed: February 1, 2016
    Publication date: March 2, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuki SEKINO, Takashi IZUMIDA, Nobutoshi AOKI
  • Patent number: 8532972
    Abstract: According to one embodiment, a method of simulating a manufacturing process of a structure including adjacent components, the method includes causing a computer to perform operations of: importing mesh and material data set for each component; specifying, as a calculation target, a region in a first component in which impurities are to be diffused among the components; setting a virtual film of a desired thickness in contact with the region whose material is the same as that of a second component in contact with the specified calculation target; setting boundary conditions at interface between the region and the virtual film, based on the material data; incorporating the boundary conditions into diffusion equations to solve the diffusion equations of the region and the virtual film; and bringing data on the concentration of impurities of the region obtained by the calculation into data on the structure before the specification of the region.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuki Sekino, Sanae Ito
  • Publication number: 20110230992
    Abstract: According to one embodiment, a method of simulating a manufacturing process of a structure including adjacent components, the method includes causing a computer to perform operations of: importing mesh and material data set for each component; specifying, as a calculation target, a region in a first component in which impurities are to be diffused among the components; setting a virtual film of a desired thickness in contact with the region whose material is the same as that of a second component in contact with the specified calculation target; setting boundary conditions at interface between the region and the virtual film, based on the material data; incorporating the boundary conditions into diffusion equations to solve the diffusion equations of the region and the virtual film; and bringing data on the concentration of impurities of the region obtained by the calculation into data on the structure before the specification of the region.
    Type: Application
    Filed: March 2, 2011
    Publication date: September 22, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuki SEKINO, Sanae ITO