Abstract: When there is currently no article at an upstream end of a trough of a downstream linear feeder, an upstream linear feeder is driven to operate until any article detected by an upstream article detector. In case no article is still detectable by the upstream article sensor when a predetermined period of time is passed after the upstream linear feeder starts to be driven, the upstream linear feeder is driven to operate by an increased vibration strength based on the assumption that an article(s) is being jammed or articles are being stuck together on an upstream side of the upstream linear feeder.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: An image reading system includes a terminal apparatus and an image reading apparatus that communicates data with the terminal apparatus and reads a sheet. The terminal apparatus includes an operation instruction unit that instructs the image reading apparatus to perform an operation. Either the terminal apparatus or the image reading apparatus includes a notification unit that notifies a user of completion of reading of the sheet and a next sheet instruction unit used by the user to determine whether to read a next sheet and include the next sheet in a resultant file in which the sheet is included.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: To reduce the effect on the communication performance of an antenna to secure a good communication state with respect to the antenna. An acoustic output device includes a speaker for outputting sound, a cell having one surface facing in a facing direction represented by a predetermined direction, a control board for controlling predetermined parts, and an antenna for sending and receiving signals, the antenna having at least a portion spaced from the control board and the cell. The cell and the control board are positioned side by side with each other in directions different from thicknesswise directions of the control board. The facing direction is different from the directions in which the cell and the control board are side by side with each other. The antenna is positioned side by side with at least one of the control board or the cell in the thicknesswise directions or the facing direction.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: This invention provides a rolled food that maintains a crispy texture characteristic of a rolled food immediately after deep frying for several hours after deep frying and a method for producing the same. This invention also provides an outer wrapper for a rolled food, such as a spring roll, in which a degree of polymerization of a gluten protein in the outer wrapper baked before rolling is 32.00% or higher and the breaking strength measured using a creep meter under specific conditions is 4.30 N or higher. Further, this invention provides a rolled food prepared with the use of such outer wrapper and a method for producing such outer wrapper and rolled food.

Abstract: The invention relates to particles with an average particle size of 300 to 1000 ?m, comprising a modified polyvinyl alcohol having vinyl alcohol units and structural units represented by formula (1), wherein a content of the vinyl alcohol units is 60 to 90 mol % based on the total structural units: wherein R1 represents a hydrogen atom or a methyl group. Thus, the present invention provides particles containing a modified polyvinyl alcohol having high water solubility and high affinity for a photosensitive monomer, which are highly photosensitive.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: The storage management computer according to the present invention can relatively easily configure a file sharing system for a file system. The storage management computer is provided with a calculation unit that includes at least a microprocessor and a communication interface circuit which communicates with a storage system, and the storage system is provided with a plurality of first pools for storing file data, and a plurality of second pools for storing block data corresponding to the file data. The calculation unit selects, from among the plurality of first pools, a predetermined first pool associated with one of the plurality of second pools, then selects a predetermined file system associated with the selected predetermined first pool, and configures a file sharing system for the selected predetermined file system.

Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.

Abstract: An ECU performs a process including: when a vehicle establishes a Ready-On state, selecting a CD mode; when discharging power is uncompleted and a scheduled time to return the vehicle is a time within a discharging period, setting a second target SOC as a mode switching value; and when the vehicle's power storage device has an SOC reaching the mode switching value and a surcharge imposed on a rental fee is unaccepted, switching the current control mode from the CD mode to a CS mode.

Abstract: A group to be authenticated in face authentication is efficiently registered in a system. An information processing system includes a face detection unit configured to detect a face from an image in which a plurality of faces of persons are shown, a determination unit configured to determine whether or not the face detected by the face detection unit satisfies a predetermined condition, and a registration information generation unit configured to generate registration information, the registration information being information in which a partial image of each of a plurality of faces that have been determined to satisfy the predetermined condition is associated with an identifier identifying a group to be authenticated in face authentication.

Abstract: In an apparatus for facilitating fatigue reduction of a user, a characteristic identifier identifies at least one personal characteristic item of the user, and a hot-cold stimulus controller instructs a hot-cold stimulator to apply hot and cold stimuluses to the user in accordance with a stimulus condition, and varies, based on the identified at least one personal characteristic item of the user, the stimulus condition of each of the hot stimulus and cold stimulus. The stimulus condition of each of the hot stimulus and cold stimulus include at least one of, one or more parts of the user to which the corresponding one of the hot stimulus and cold stimulus is to be applied, a temperature of the corresponding one of the hot stimulus and cold stimulus, and an application period of the corresponding one of the hot stimulus and cold stimulus to the user.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A liquid-crystal varifocal lens includes a liquid crystal lens, and an ultrasonic transducer for generating an ultrasonic wave with a frequency that matches a resonant frequency of the liquid crystal lens. The ultrasonic transducer generates flexural oscillation in the liquid crystal lens such that the flexural oscillation has a vibration intensity decreasing continuously from the center to the circumference of a liquid crystal layer, whereby the thickness of the liquid crystal layer is changed, with the result that the orientation of the liquid crystal molecules is changed.

Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.

Abstract: In testing a component-set whole process which includes a plurality of components and in which the order of execution of the plurality of components is defined, a computer system exports, to a storage resource, an input package for at least one component to be executed. Each of the plurality of components is a module of a significant process as a set of one or more processing steps and independent of any other components. Each input package includes an input value of a component that corresponds to the input package. The computer system imports an exported input package of a component to be debugged into the component to be debugged in order to execute the component to be debugged, without executing a component the order of which precedes the order N (where N is a natural number) of the component to be debugged.