Abstract: According to one embodiment, a semiconductor storage device includes strings each with a first select transistor, memory cell transistors, and a second select transistor connected in series. Word lines are provided, each connected to memory cell transistors in a same position across the strings. A bit line is connected in common to a first end of each of the strings. A source line is connected in common to a second end of each of the strings. A control circuit is configured to perform an erase operation on strings. The control circuit adjusts, for each of the strings, either an application time of a first voltage applied to a gate of the first select transistor of the respective string in the erase operation or a voltage level of the first voltage applied to the gate of the first select transistor of the respective string in the erase operation.

Abstract: According to one embodiment, a semiconductor storage device includes strings each with a first select transistor, memory cell transistors, and a second select transistor connected in series. Word lines are provided, each connected to memory cell transistors in a same position across the strings. A bit line is connected in common to a first end of each of the strings. A source line is connected in common to a second end of each of the strings. A control circuit is configured to perform an erase operation on strings. The control circuit adjusts, for each of the strings, either an application time of a first voltage applied to a gate of the first select transistor of the respective string in the erase operation or a voltage level of the first voltage applied to the gate of the first select transistor of the respective string in the erase operation.

Abstract: A semiconductor memory device includes a substrate, a plurality of bit lines extending in a first direction parallel to a main surface of the substrate, a plurality of selection gates extending in a second direction perpendicular to the first direction, and a contact region between the selection gates on the substrate and includes a plurality of contacts respectively formed under the bit lines. The contact region is formed so that N (N?3) contacts are disposed under the N adjacent bit lines on a straight line that is not parallel to the first and second directions. A first dummy contact is located under a first bit line of the N adjacent bit lines, and a second dummy contact located under the N-th bit line among the N adjacent bit lines.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a first region and a second region, a first insulating layer provided above the semiconductor layer, an extending first contact electrode, having a sidewall surrounded with the first insulating layer, and electrically connected to a first element provided in the first region, an extending second contact electrode, having a sidewall surrounded with the first insulating layer, and electrically connected to a second element provided in the second region, an extending first interconnection layer connected to an upper end of the first contact electrode, and having a sidewall surrounded with the first insulating layer, and an extending second interconnection layer connected to an upper end of the second contact electrode, having a sidewall surrounded with the first insulating layer, and having a line width wider than a line width of the first interconnection layer.