Abstract: A kickback current is suppressed so as not to generate a deviation in a signal that outputs a comparison result.

Abstract: To reduce a circuit scale in a successive approximation register analog to digital converter (SARADC) provided with a circuit that cancels a ripple. A digital-to-analog converter generates at least one of a pair of analog signals according to a predetermined control signal. A comparator compares the pair of analog signals and outputs a comparison result. A logic circuit generates a control signal on the basis of the comparison result. A plurality of switches opens and closes a path between one of a source and a drain of each of a plurality of positive-side transistors having different sizes and a plurality of negative-side transistors having different sizes and an output terminal of the comparator on the basis of the control signal. A positive-side common capacitor has one end connected to a node of a predetermined positive-side reference voltage, and has the other end connected in common to each of the gates of the plurality of positive-side transistors.

Abstract: A kickback current is suppressed so as not to generate a deviation in a signal that outputs a comparison result.

Abstract: To suppress the off-leakage current in a switch circuit when the switch circuit is controlled to be in an OFF state. First and second path switches are switch circuits connected in series. The first and second path switches are controlled to be in either an ON state of an OFF state at the same time. When the first and second path switches are controlled to be in the OFF state, the voltage supply circuit supplies the same voltage to the connection portion of the first and second path switches and the input portion of the first path switch. In this way, the same voltage is supplied to both ends of the first path switch.

Abstract: A detectable range is increased in a radar apparatus that measures a distance from a round-trip time of a sound wave. A transmitting unit transmits a plurality of sound waves including different frequency components in order. A receiving unit receives reflected waves obtained as the plurality of sound waves is reflected. An analyzing unit analyzes a frequency component of each of the reflected waves and identifies, for each reflected wave, the sound wave corresponding to the reflected wave among the plurality of sound waves on the basis of the analysis result. A ranging unit acquires a distance corresponding to a period of time from a transmission time of the sound wave corresponding to the reflected wave to a reception time of the reflected wave.

Abstract: A biological information measurement apparatus according to an embodiment of the present disclosure includes one or a plurality of measurement channels to be brought into contact with a biological body, and a reference channel to be brought into contact with the biological body. The biological information measurement apparatus further includes a differential circuit that generates a biological signal corresponding to a difference between a measurement signal obtained from the measurement channel and a reference signal obtained from the reference channel, and a switch mechanism that switches contact impedance between the biological body and each of the measurement channel and the reference channel.

Abstract: The present technology relates to a signal processing device, a signal processing method, a program, and a measurement device which are capable of saving electric power while reducing a cost. The signal processing device mixes a periodical periodic signal with a reflection signal corresponding to reflection light reflected at a subject and filters, by a low pass filter (LPF), a mixed signal acquired by mixing the reflection signal with the periodic signal. The present technology is applicable to, for example, a measurement device that non-invasively measures a blood flow velocity under the skin by irradiating a human body with light and receiving reflection light reflected at the human body.

Abstract: To reduce power consumption of an analog-to-digital converter in which a comparator is provided. An analog-to-digital converter includes a comparator and a mode control unit. The comparator is configured to generate a comparison result by comparing an analog signal to a threshold indicating a boundary of a predetermined range in a determination mode and convert the analog signal into a digital signal in a conversion mode. The mode control unit is configured to transition the determination mode to the conversion mode in a case in which the comparison result indicating that the analog signal is not within the predetermined range is generated.

Abstract: A detectable range is increased in a radar apparatus that measures a distance from a round-trip time of a sound wave. A transmitting unit transmits a plurality of sound waves including different frequency components in order. A receiving unit receives reflected waves obtained as the plurality of sound waves is reflected. An analyzing unit analyzes a frequency component of each of the reflected waves and identifies, for each reflected wave, the sound wave corresponding to the reflected wave among the plurality of sound waves on the basis of the analysis result. A ranging unit acquires a distance corresponding to a period of time from a transmission time of the sound wave corresponding to the reflected wave to a reception time of the reflected wave.

Abstract: An operation speed of a voltage conversion circuit is improved without increasing an output level of the voltage conversion circuit. The voltage conversion circuit is provided with a high-voltage side transistor and a gate control unit. In this voltage conversion circuit, the high-voltage side transistor outputs a predetermined high voltage higher than a predetermined reference voltage. Also, in the voltage conversion circuit, the gate control unit generates a predetermined control voltage higher than a predetermined high voltage from an input signal and applies the same between a gate and a source of the high-voltage side transistor, thereby allowing the high-voltage side transistor to output a predetermined high voltage.

Abstract: The present technology relates to a semiconductor device that includes a level shifter circuit that performs level conversion on a digital signal output from a predetermined block and outputs a resultant signal to another block that operates by a power source different from the power source of the predetermined block, and a power source monitoring circuit that controls an operation of the level shifter circuit. The power source monitoring circuit stops an operation of the level shifter circuit on the basis of a status of the power source that supplies power to the predetermined block and a standby control signal for controlling an operation status of the other block. Further, the power source monitoring circuit is provided with a transistor on a path of a steady-state current, and the steady-state current is inhibited from flowing in accordance with the standby control signal.

Abstract: To reduce power consumption of an analog-to-digital converter in which a comparator is provided. An analog-to-digital converter includes a comparator and a mode control unit. The comparator is configured to generate a comparison result by comparing an analog signal to a threshold indicating a boundary of a predetermined range in a determination mode and convert the analog signal into a digital signal in a conversion mode. The mode control unit is configured to transition the determination mode to the conversion mode in a case in which the comparison result indicating that the analog signal is not within the predetermined range is generated.

Abstract: An operation speed of a voltage conversion circuit is improved without increasing an output level of the voltage conversion circuit. The voltage conversion circuit is provided with a high-voltage side transistor and a gate control unit. In this voltage conversion circuit, the high-voltage side transistor outputs a predetermined high voltage higher than a predetermined reference voltage. Also, in the voltage conversion circuit, the gate control unit generates a predetermined control voltage higher than a predetermined high voltage from an input signal and applies the same between a gate and a source of the high-voltage side transistor, thereby allowing the high-voltage side transistor to output a predetermined high voltage.

Abstract: The present technology relates to a power source monitoring circuit, a power on reset circuit, and a semiconductor device that are capable of reducing a steady-state current. The semiconductor device includes a level shifter circuit that performs level conversion on a digital signal output from a predetermined block and outputs a resultant signal to another block that operates by a power source different from the power source of the predetermined block, and a power source monitoring circuit that controls an operation of the level shifter circuit. The power source monitoring circuit stops an operation of the level shifter circuit on the basis of a status of the power source that supplies power to the predetermined block and a standby control signal for controlling an operation status of the other block.

Abstract: A voltage conversion circuit includes: a first voltage conversion unit configured to perform voltage conversion on an input signal, the voltage conversion causing a predetermined delay time, and supply a resultant signal as a first converted signal; a second voltage conversion unit configured to perform voltage conversion on the input signal, the voltage conversion causing a delay time that is different from the predetermined delay time, and supply a resultant signal as a second converted signal; and an output unit configured to generate and output an output signal corresponding to the first and second converted signals in a matching period of time in which voltages of the first converted signal and the second converted signal are matched with each other, and continuously output the output signal in a period of time excluding the matching period of time, the output signal being output in the matching period of time.

Abstract: A voltage conversion circuit includes: a first voltage conversion unit configured to perform voltage conversion on an input signal, the voltage conversion causing a predetermined delay time, and supply a resultant signal as a first converted signal; a second voltage conversion unit configured to perform voltage conversion on the input signal, the voltage conversion causing a delay time that is different from the predetermined delay time, and supply a resultant signal as a second converted signal; and an output unit configured to generate and output an output signal corresponding to the first and second converted signals in a matching period of time in which voltages of the first converted signal and the second converted signal are matched with each other, and continuously output the output signal in a period of time excluding the matching period of time, the output signal being output in the matching period of time.

Abstract: A phase-locked loop circuit includes: a phase and frequency comparing section configured to compare a phase of an external reference clock signal with a phase of a comparison clock signal, and generate an error signal corresponding to a result of comparison; an oscillating section configured to generate an internal clock signal of an oscillation frequency corresponding to the error signal; a frequency dividing section configured to generate the comparison clock signal by frequency-dividing the internal clock signal by a predetermined frequency dividing ratio; an oscillator control section configured to generate an oscillation control signal for controlling frequency of the internal clock signal output from the oscillating section on a basis of the error signal; and a frequency divider control section configured to generate a frequency division control signal for controlling a bias current of the frequency dividing section on a basis of the error signal.

Abstract: A phase-locked loop circuit includes: a phase and frequency comparing section configured to compare a phase of an external reference clock signal with a phase of a comparison clock signal, and generate an error signal corresponding to a result of comparison; an oscillating section configured to generate an internal clock signal of an oscillation frequency corresponding to the error signal; a frequency dividing section configured to generate the comparison clock signal by frequency-dividing the internal clock signal by a predetermined frequency dividing ratio; an oscillator control section configured to generate an oscillation control signal for controlling frequency of the internal clock signal output from the oscillating section on a basis of the error signal; and a frequency divider control section configured to generate a frequency division control signal for controlling a bias current of the frequency dividing section on a basis of the error signal.