Patents by Inventor Yuki YAGYU
Yuki YAGYU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11322859Abstract: An electronic device includes a connection unit having an electric wire and an insulation-displacement terminal. The electric wire includes a conductor and an insulation coating on an outer periphery of the conductor. The insulation-displacement terminal includes two beams facing each other in a first direction to define a slot, and receives the electric wire in the slot to have an electrical connection. The insulation-displacement terminal includes an introduction part defining an opening of the slot, a scrape part for scraping the insulation coating from the electric wire, and a fix part fixing the electric wire in order along a second direction from the opening to an innermost of the slot. The thickness of the scrape part gradually increases toward the second direction so that as the electric wire advances through the scrape part along the second direction the width of the conductor to be scraped gradually increases.Type: GrantFiled: February 28, 2020Date of Patent: May 3, 2022Assignee: DENSO CORPORATIONInventor: Yuki Yagyu
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Patent number: 11128069Abstract: An electronic device includes a press-fit terminal and a recess. The press-fit terminal includes a bar portion and a press-fit deformation portion. The press-fit deformation portion is provided at an end of the bar portion. The press-fit deformation portion is deformed when inserted into an insertion hole of a circuit board. The recess is provided in the press-fit deformation portion and recessed from a surface of the press-fit deformation portion.Type: GrantFiled: February 28, 2020Date of Patent: September 21, 2021Assignee: DENSO CORPORATIONInventor: Yuki Yagyu
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Publication number: 20200303843Abstract: An electronic device includes a connection unit. The connection unit includes an electric wire and an insulation-displacement terminal. The electric wire includes a conductor and an insulation coating on an outer periphery of the conductor. The insulation-displacement terminal includes two beams facing each other in a first direction to define a slot between the two beams, and receives the electric wire in the slot to have an electrical connection. The insulation-displacement terminal includes an introduction part defining an opening of the slot, a scrape part for scraping the insulation coating from the electric wire, and a fix part fixing the electric wire in order along a second direction from the opening to an innermost of the slot.Type: ApplicationFiled: February 28, 2020Publication date: September 24, 2020Inventor: Yuki YAGYU
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Publication number: 20200287305Abstract: An electronic device includes a press-fit terminal and a recess. The press-fit terminal includes a bar portion and a press-fit deformation portion. The press-fit deformation portion is provided at an end of the bar portion. The press-fit deformation portion is deformed when inserted into an insertion hole of a circuit board. The recess is provided in the press-fit deformation portion and recessed from a surface of the press-fit deformation portion.Type: ApplicationFiled: February 28, 2020Publication date: September 10, 2020Inventor: Yuki YAGYU
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Patent number: 10680360Abstract: A press-fit terminal includes a bar part and a deformation part provided at an end portion of the bar part. The deformation part includes a recess, a front boundary portion and a rear boundary portion. The recess is provided between a front end portion of the deformation part and the end portion of the bar part. The front boundary portion defines a boundary between the recess and a surface of the deformation part adjacent to the front end portion of the deformation part. The rear boundary portion defines a boundary between the recess and the surface of the deformation part adjacent to the end portion of the bar part.Type: GrantFiled: March 29, 2019Date of Patent: June 9, 2020Assignee: DENSO CORPORATIONInventor: Yuki Yagyu
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Patent number: 10535931Abstract: A wire connection device includes an electrical wire, an insulation displacement terminal and a stress relaxation member. The electrical wire includes a conductor and an insulation coating on an outer periphery of the conductor. The insulation displacement terminal has a slot in which the electrical wire is fitted. The insulation displacement terminal is connected to the electrical wire by both side portions of the slot being in direct contact with the conductor and pressing the conductor elastically and plastically. The stress relaxation member is fitted in the slot of the insulation displacement terminal to suppress deterioration of a stress applied to the electrical wire.Type: GrantFiled: September 14, 2018Date of Patent: January 14, 2020Assignee: DENSO CORPORATIONInventor: Yuki Yagyu
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Publication number: 20190312367Abstract: A press-fit terminal includes a bar part and a deformation part provided at an end portion of the bar part. The deformation part includes a recess, a front boundary portion and a rear boundary portion. The recess is provided between a front end portion of the deformation part and the end portion of the bar part. The front boundary portion defines a boundary between the recess and a surface of the deformation part adjacent to the front end portion of the deformation part. The rear boundary portion defines a boundary between the recess and the surface of the deformation part adjacent to the end portion of the bar part.Type: ApplicationFiled: March 29, 2019Publication date: October 10, 2019Inventor: Yuki Yagyu
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Patent number: 10381318Abstract: The present invention: makes it possible to improve the reliability of a semiconductor device; and provides a method of manufacturing the semiconductor device comprising the steps of (a) providing a semiconductor wafer having a pad electrode, a first conductive layer comprised of copper, a photoresist film, and a second conductive layer comprised of gold, (b) forming a protective film comprised of iodine on the surface of the second conductive layer, (c) removing the photoresist film, (d) irradiating the protective film with argon ions and removing the protective film, and (e) bringing a part of a bonding wire into contact with the surface of the second conductive layer.Type: GrantFiled: May 4, 2018Date of Patent: August 13, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yuki Yagyu
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Patent number: 10347604Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.Type: GrantFiled: February 21, 2018Date of Patent: July 9, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuki Yagyu, Seiya Isozaki
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Publication number: 20190140369Abstract: A wire connection device includes an electrical wire, an insulation displacement terminal and a stress relaxation member. The electrical wire includes a conductor and an insulation coating on an outer periphery of the conductor. The insulation displacement terminal has a slot in which the electrical wire is fitted. The insulation displacement terminal is connected to the electrical wire by both side portions of the slot being in direct contact with the conductor and pressing the conductor elastically and plastically. The stress relaxation member is fitted in the slot of the insulation displacement terminal to suppress deterioration of a stress applied to the electrical wire.Type: ApplicationFiled: September 14, 2018Publication date: May 9, 2019Inventor: Yuki YAGYU
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Publication number: 20180350759Abstract: The present invention: makes it possible to improve the reliability of a semiconductor device; and provides a method of manufacturing the semiconductor device comprising the steps of (a) providing a semiconductor wafer having a pad electrode, a first conductive layer comprised of copper, a photoresist film, and a second conductive layer comprised of gold, (b) forming a protective film comprised of iodine on the surface of the second conductive layer, (c) removing the photoresist film, (d) irradiating the protective film with argon ions and removing the protective film, and (e) bringing a part of a bonding wire into contact with the surface of the second conductive layer.Type: ApplicationFiled: May 4, 2018Publication date: December 6, 2018Applicant: Renesas Electronics CorporationInventor: Yuki YAGYU
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Patent number: 10128130Abstract: A compact and high-reliability semiconductor device is implemented. The bonding wires situated in the vicinity of a gate, and the bonding wires situated in the vicinity of a vent facing to the gate across the center of a semiconductor chip in a molding step have a loop shape falling inwardly of the semiconductor chip, have a weaker pulling force (tension) than those of other bonding wires, and are loosely stretched with a margin. The bonding wires situated in the vicinity of the gate in the molding step are, for example, a first wire and a fifth wire to be connected with a first electrode pad and a fifth electrode pad, respectively. Whereas, the bonding wires situated in the vicinity of the vent in the molding step are, for example, a third wire and a seventh wire to be connected with a third electrode pad and a seventh electrode pad, respectively.Type: GrantFiled: December 1, 2017Date of Patent: November 13, 2018Assignee: Renesas Electronics CorporationInventor: Yuki Yagyu
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Publication number: 20180277511Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.Type: ApplicationFiled: February 21, 2018Publication date: September 27, 2018Applicant: Renesas Electronics CorporationInventors: Yuki YAGYU, Seiya ISOZAKI
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Publication number: 20180182644Abstract: A compact and high-reliability semiconductor device is implemented. The bonding wires situated in the vicinity of a gate, and the bonding wires situated in the vicinity of a vent facing to the gate across the center of a semiconductor chip in a molding step have a loop shape falling inwardly of the semiconductor chip, have a weaker pulling force (tension) than those of other bonding wires, and are loosely stretched with a margin. The bonding wires situated in the vicinity of the gate in the molding step are, for example, a first wire and a fifth wire to be connected with a first electrode pad and a fifth electrode pad, respectively. Whereas, the bonding wires situated in the vicinity of the vent in the molding step are, for example, a third wire and a seventh wire to be connected with a third electrode pad and a seventh electrode pad, respectively.Type: ApplicationFiled: December 1, 2017Publication date: June 28, 2018Inventor: Yuki YAGYU
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Patent number: 9972598Abstract: Reliability of a semiconductor device is improved. A wire bonding step includes a step of exposing a wire and a pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of a ball portion, and forming a second hydroxyl layer on a surface of the pad electrode, a first bonding step of temporarily joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and after the first bonding step, a step of actually joining the ball portion to the pad electrode by performing a heat treatment on a semiconductor chip and a base material.Type: GrantFiled: July 1, 2017Date of Patent: May 15, 2018Assignee: Renesas Electronics CorporationInventor: Yuki Yagyu
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Publication number: 20180082977Abstract: Reliability of a semiconductor device is improved. A wire bonding step includes a step of exposing a wire and a pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of a ball portion, and forming a second hydroxyl layer on a surface of the pad electrode, a first bonding step of temporarily joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and after the first bonding step, a step of actually joining the ball portion to the pad electrode by performing a heat treatment on a semiconductor chip and a base material.Type: ApplicationFiled: July 1, 2017Publication date: March 22, 2018Inventor: Yuki YAGYU
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Publication number: 20160197050Abstract: A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.Type: ApplicationFiled: March 16, 2016Publication date: July 7, 2016Inventors: Toshihiko AKIBA, Akihiro TOBITA, Yuki YAGYU
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Patent number: 9293436Abstract: A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.Type: GrantFiled: May 13, 2015Date of Patent: March 22, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshihiko Akiba, Akihiro Tobita, Yuki Yagyu
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Publication number: 20150333030Abstract: A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.Type: ApplicationFiled: May 13, 2015Publication date: November 19, 2015Inventors: Toshihiko AKIBA, Akihiro TOBITA, Yuki YAGYU