Patents by Inventor Yuki YAGYU

Yuki YAGYU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136439
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, an element region, and fin transistors. The substrate includes a principal surface. The semiconductor layer is formed as a surface layer or on the principal surface of the substrate, the surface layer being the principal surface of the substrate. The semiconductor layer has a crystal structure in which an angle between two of crystal orientations with equivalent relationships on a crystal plane having a correspondence with the principal surface of the substrate is 60 degrees or 120 degrees. The element region includes unit element regions formed on the principal surface of the substrate. The fin transistors are formed in the semiconductor layer, in the respective unit element regions. The fin transistors radially extend from a center toward an outer periphery of the element region. Adjacent two of the fin transistors have a spacing with a 60° angle or a 120° angle.
    Type: Application
    Filed: March 22, 2021
    Publication date: April 25, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuki TAKIGUCHI, Eiji YAGYU, Kunihiko NISHIMURA, Hisashi SAITO, Takahiro YAMADA, Daisuke TSUNAMI, Marika NAKAMURA, Masanao ITO
  • Patent number: 11961765
    Abstract: The present invention relates to a method for manufacturing a semiconductor substrate, including: (a) preparing an epitaxial substrate having a nitride semiconductor layer formed on a first main surface of a growth substrate and preparing a first support substrate, forming a resin adhesive layer between the first main surface of the growth substrate and a first main surface of the first support substrate, and bonding the epitaxial substrate to the first support substrate; (b) thinning a second main surface of the growth substrate; (c) forming a first protective thin film layer on the thinned growth substrate; (d) forming a second protective thin film layer on the first support substrate; (e) removing the thinned growth substrate; (f) bonding a second support substrate onto the nitride semiconductor layer; and (g) removing the first support substrate and the resin adhesive layer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: April 16, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shuichi Hiza, Kunihiko Nishimura, Masahiro Fujikawa, Yuki Takiguchi, Eiji Yagyu
  • Patent number: 11322859
    Abstract: An electronic device includes a connection unit having an electric wire and an insulation-displacement terminal. The electric wire includes a conductor and an insulation coating on an outer periphery of the conductor. The insulation-displacement terminal includes two beams facing each other in a first direction to define a slot, and receives the electric wire in the slot to have an electrical connection. The insulation-displacement terminal includes an introduction part defining an opening of the slot, a scrape part for scraping the insulation coating from the electric wire, and a fix part fixing the electric wire in order along a second direction from the opening to an innermost of the slot. The thickness of the scrape part gradually increases toward the second direction so that as the electric wire advances through the scrape part along the second direction the width of the conductor to be scraped gradually increases.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 3, 2022
    Assignee: DENSO CORPORATION
    Inventor: Yuki Yagyu
  • Patent number: 11128069
    Abstract: An electronic device includes a press-fit terminal and a recess. The press-fit terminal includes a bar portion and a press-fit deformation portion. The press-fit deformation portion is provided at an end of the bar portion. The press-fit deformation portion is deformed when inserted into an insertion hole of a circuit board. The recess is provided in the press-fit deformation portion and recessed from a surface of the press-fit deformation portion.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: September 21, 2021
    Assignee: DENSO CORPORATION
    Inventor: Yuki Yagyu
  • Publication number: 20200303843
    Abstract: An electronic device includes a connection unit. The connection unit includes an electric wire and an insulation-displacement terminal. The electric wire includes a conductor and an insulation coating on an outer periphery of the conductor. The insulation-displacement terminal includes two beams facing each other in a first direction to define a slot between the two beams, and receives the electric wire in the slot to have an electrical connection. The insulation-displacement terminal includes an introduction part defining an opening of the slot, a scrape part for scraping the insulation coating from the electric wire, and a fix part fixing the electric wire in order along a second direction from the opening to an innermost of the slot.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 24, 2020
    Inventor: Yuki YAGYU
  • Publication number: 20200287305
    Abstract: An electronic device includes a press-fit terminal and a recess. The press-fit terminal includes a bar portion and a press-fit deformation portion. The press-fit deformation portion is provided at an end of the bar portion. The press-fit deformation portion is deformed when inserted into an insertion hole of a circuit board. The recess is provided in the press-fit deformation portion and recessed from a surface of the press-fit deformation portion.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 10, 2020
    Inventor: Yuki YAGYU
  • Patent number: 10680360
    Abstract: A press-fit terminal includes a bar part and a deformation part provided at an end portion of the bar part. The deformation part includes a recess, a front boundary portion and a rear boundary portion. The recess is provided between a front end portion of the deformation part and the end portion of the bar part. The front boundary portion defines a boundary between the recess and a surface of the deformation part adjacent to the front end portion of the deformation part. The rear boundary portion defines a boundary between the recess and the surface of the deformation part adjacent to the end portion of the bar part.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 9, 2020
    Assignee: DENSO CORPORATION
    Inventor: Yuki Yagyu
  • Patent number: 10535931
    Abstract: A wire connection device includes an electrical wire, an insulation displacement terminal and a stress relaxation member. The electrical wire includes a conductor and an insulation coating on an outer periphery of the conductor. The insulation displacement terminal has a slot in which the electrical wire is fitted. The insulation displacement terminal is connected to the electrical wire by both side portions of the slot being in direct contact with the conductor and pressing the conductor elastically and plastically. The stress relaxation member is fitted in the slot of the insulation displacement terminal to suppress deterioration of a stress applied to the electrical wire.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: January 14, 2020
    Assignee: DENSO CORPORATION
    Inventor: Yuki Yagyu
  • Publication number: 20190312367
    Abstract: A press-fit terminal includes a bar part and a deformation part provided at an end portion of the bar part. The deformation part includes a recess, a front boundary portion and a rear boundary portion. The recess is provided between a front end portion of the deformation part and the end portion of the bar part. The front boundary portion defines a boundary between the recess and a surface of the deformation part adjacent to the front end portion of the deformation part. The rear boundary portion defines a boundary between the recess and the surface of the deformation part adjacent to the end portion of the bar part.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 10, 2019
    Inventor: Yuki Yagyu
  • Patent number: 10381318
    Abstract: The present invention: makes it possible to improve the reliability of a semiconductor device; and provides a method of manufacturing the semiconductor device comprising the steps of (a) providing a semiconductor wafer having a pad electrode, a first conductive layer comprised of copper, a photoresist film, and a second conductive layer comprised of gold, (b) forming a protective film comprised of iodine on the surface of the second conductive layer, (c) removing the photoresist film, (d) irradiating the protective film with argon ions and removing the protective film, and (e) bringing a part of a bonding wire into contact with the surface of the second conductive layer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuki Yagyu
  • Patent number: 10347604
    Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: July 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Yagyu, Seiya Isozaki
  • Publication number: 20190140369
    Abstract: A wire connection device includes an electrical wire, an insulation displacement terminal and a stress relaxation member. The electrical wire includes a conductor and an insulation coating on an outer periphery of the conductor. The insulation displacement terminal has a slot in which the electrical wire is fitted. The insulation displacement terminal is connected to the electrical wire by both side portions of the slot being in direct contact with the conductor and pressing the conductor elastically and plastically. The stress relaxation member is fitted in the slot of the insulation displacement terminal to suppress deterioration of a stress applied to the electrical wire.
    Type: Application
    Filed: September 14, 2018
    Publication date: May 9, 2019
    Inventor: Yuki YAGYU
  • Publication number: 20180350759
    Abstract: The present invention: makes it possible to improve the reliability of a semiconductor device; and provides a method of manufacturing the semiconductor device comprising the steps of (a) providing a semiconductor wafer having a pad electrode, a first conductive layer comprised of copper, a photoresist film, and a second conductive layer comprised of gold, (b) forming a protective film comprised of iodine on the surface of the second conductive layer, (c) removing the photoresist film, (d) irradiating the protective film with argon ions and removing the protective film, and (e) bringing a part of a bonding wire into contact with the surface of the second conductive layer.
    Type: Application
    Filed: May 4, 2018
    Publication date: December 6, 2018
    Applicant: Renesas Electronics Corporation
    Inventor: Yuki YAGYU
  • Patent number: 10128130
    Abstract: A compact and high-reliability semiconductor device is implemented. The bonding wires situated in the vicinity of a gate, and the bonding wires situated in the vicinity of a vent facing to the gate across the center of a semiconductor chip in a molding step have a loop shape falling inwardly of the semiconductor chip, have a weaker pulling force (tension) than those of other bonding wires, and are loosely stretched with a margin. The bonding wires situated in the vicinity of the gate in the molding step are, for example, a first wire and a fifth wire to be connected with a first electrode pad and a fifth electrode pad, respectively. Whereas, the bonding wires situated in the vicinity of the vent in the molding step are, for example, a third wire and a seventh wire to be connected with a third electrode pad and a seventh electrode pad, respectively.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: November 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Yagyu
  • Publication number: 20180277511
    Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.
    Type: Application
    Filed: February 21, 2018
    Publication date: September 27, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Yuki YAGYU, Seiya ISOZAKI
  • Publication number: 20180182644
    Abstract: A compact and high-reliability semiconductor device is implemented. The bonding wires situated in the vicinity of a gate, and the bonding wires situated in the vicinity of a vent facing to the gate across the center of a semiconductor chip in a molding step have a loop shape falling inwardly of the semiconductor chip, have a weaker pulling force (tension) than those of other bonding wires, and are loosely stretched with a margin. The bonding wires situated in the vicinity of the gate in the molding step are, for example, a first wire and a fifth wire to be connected with a first electrode pad and a fifth electrode pad, respectively. Whereas, the bonding wires situated in the vicinity of the vent in the molding step are, for example, a third wire and a seventh wire to be connected with a third electrode pad and a seventh electrode pad, respectively.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 28, 2018
    Inventor: Yuki YAGYU
  • Patent number: 9972598
    Abstract: Reliability of a semiconductor device is improved. A wire bonding step includes a step of exposing a wire and a pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of a ball portion, and forming a second hydroxyl layer on a surface of the pad electrode, a first bonding step of temporarily joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and after the first bonding step, a step of actually joining the ball portion to the pad electrode by performing a heat treatment on a semiconductor chip and a base material.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: May 15, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Yagyu
  • Publication number: 20180082977
    Abstract: Reliability of a semiconductor device is improved. A wire bonding step includes a step of exposing a wire and a pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of a ball portion, and forming a second hydroxyl layer on a surface of the pad electrode, a first bonding step of temporarily joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and after the first bonding step, a step of actually joining the ball portion to the pad electrode by performing a heat treatment on a semiconductor chip and a base material.
    Type: Application
    Filed: July 1, 2017
    Publication date: March 22, 2018
    Inventor: Yuki YAGYU
  • Publication number: 20160197050
    Abstract: A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.
    Type: Application
    Filed: March 16, 2016
    Publication date: July 7, 2016
    Inventors: Toshihiko AKIBA, Akihiro TOBITA, Yuki YAGYU
  • Patent number: 9293436
    Abstract: A manufacturing method of a BGA, includes the steps of: providing a semiconductor chip having electrode pads; and removing a natural oxide film formed on the surface of each of the electrode pads. Further, a first film comprised of a conductive member is formed on the surface of the electrode pad exposed by removing the natural oxide film, a wire is connected with the first film, and part of the wire is brought into contact with the electrode pad to form an alloy layer at the interface between the wire and the electrode pad. The crystal structure of the first film is comprised of a body-centered cubic lattice or a hexagonal close-packed lattice. The cost of the semiconductor device can be reduced while the bonding reliability of wire bonding of the semiconductor device is ensured.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: March 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiko Akiba, Akihiro Tobita, Yuki Yagyu