Patents by Inventor Yuki YANAGIHARA

Yuki YANAGIHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220290749
    Abstract: A vehicle drive device is provided that can suppress the increase in dimension in the radial direction while ensuring a sufficient speed reduction ratio. Two driving force sources are arranged on a first axis, two output members are arranged on a second axis, two counter gear mechanisms are arranged on a third axis. A planetary gear mechanism is configured to transmit rotation from the two counter gear mechanisms to the output members, and is disposed so as to overlap with both of the two counter gear mechanisms as seen in an axial direction along and axial direction.
    Type: Application
    Filed: August 28, 2020
    Publication date: September 15, 2022
    Applicants: AISIN CORPORATION, MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Toshihisa MIZUTANI, Kenta KATAOKA, Taiki OWARI, Hiroaki OSANAI, Daiki SUYAMA, Hiroshi KATO, Yuki YANAGIHARA, Naoki TAKAHASHI, Kiminobu TERAO, Takuya OGASAWARA, Yosuke MORIMOTO
  • Patent number: 11088697
    Abstract: A phase-frequency comparator compares a reference signal with an output signal from a variable frequency divider, and outputs an up signal of frequency and a down signal of frequency depending on results of the comparison. An AND circuit performs an AND operation between the up signal and the down signal, and outputs a result of the operation as a retiming si al CLKretime. A flip-flop circuit holds an output signal from a frequency control circuit at timing of the output signal from the AND circuit, and outputs the held output signal. At ?? modulator determines a division ratio for the variable frequency divider on the basis of the output from the flip-flop circuit.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: August 10, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji Tsutsumi, Yuki Yanagihara, Mitsuhiro Shimozawa
  • Patent number: 10659062
    Abstract: A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: May 19, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuki Yanagihara, Koji Tsutsumi, Mitsuhiro Shimozawa
  • Publication number: 20200083894
    Abstract: A phase-frequency comparator compares a reference signal with an output signal from a variable frequency divider, and outputs an up signal of frequency and a down signal of frequency depending on results of the comparison. An AND circuit performs an AND operation between the up signal and the down signal, and outputs a result of the operation as a retiming si al CLKretime. A flip-flop circuit holds an output signal from a frequency control circuit at timing of the output signal from the AND circuit, and outputs the held output signal. At ?? modulator determines a division ratio for the variable frequency divider on the basis of the output from the flip-flop circuit.
    Type: Application
    Filed: July 4, 2017
    Publication date: March 12, 2020
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji TSUTSUMI, Yuki YANAGIHARA, Mitsuhiro SHIMOZAWA
  • Patent number: 10461756
    Abstract: A first frequency accumulator (7a) operates using an output signal of a variable frequency divider (3) as a clock. A second frequency accumulator (7b) operates using a reference signal from a reference signal source (1) as a clock. A comparison operating circuit (11) compares the output values of the first frequency accumulator (7a) and the second frequency accumulator (7b), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6) depending on the parameter output from the comparison operating circuit (11).
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: October 29, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji Tsutsumi, Yuki Yanagihara, Mitsuhiro Shimozawa
  • Publication number: 20190305781
    Abstract: A first frequency accumulator (7a) operates using an output signal of a variable frequency divider (3) as a clock. A second frequency accumulator (7b) operates using a reference signal from a reference signal source (1) as a clock. A comparison operating circuit (11) compares the output values of the first frequency accumulator (7a) and the second frequency accumulator (7b), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6) depending on the parameter output from the comparison operating circuit (11).
    Type: Application
    Filed: December 19, 2016
    Publication date: October 3, 2019
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji TSUTSUMI, Yuki YANAGIHARA, Mitsuhiro SHIMOZAWA
  • Publication number: 20190296749
    Abstract: A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.
    Type: Application
    Filed: December 15, 2016
    Publication date: September 26, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuki YANAGIHARA, Koji TSUTSUMI, Mitsuhiro SHIMOZAWA
  • Patent number: 10411714
    Abstract: A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: September 10, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuki Yanagihara, Koji Tsutsumi
  • Publication number: 20190036533
    Abstract: A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.
    Type: Application
    Filed: March 16, 2016
    Publication date: January 31, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuki YANAGIHARA, Koji TSUTSUMI