Abstract: A PLL circuit has (i) a counter which divides a frequency of a VCO output whose frequency has been divided by a frequency divider and (ii) a memory which stores plural patterns of set cycles of the counter. The memory reads out one of the set cycles designated by a selection signal inputted through a serial bus (SB) from an outside of the PLL circuit. The set cycle, read out from the memory, which has a large amount of data, is inputted through a parallel bus (PB) into the counter, so that it hardly takes time to set a cycle for the counter. Further, even when the number of bits of the counter increases, the setting time is not lengthened.

Abstract: A circuit board has circuitry including a first part and a second part connected to each other via a given first dividing plane. After the circuitry is divided by the first dividing plane, the circuitry can be restored by reconnecting the first part and the second part. The circuit board further has: first division assisting means for facilitating division of the circuit board; and first connection assisting means for facilitating reconnection of the first part and the second part. This eliminates the need to prepare different circuit boards having different specifications, making it possible to efficiently incorporate the circuit board in as many types of devices as possible.

Abstract: The subject invention provides a radio-frequency receiving apparatus including a built-in test signal source for producing a radio-frequency test signal. This structure achieves cost reduction, as well as an increase of the yield, since an expensive test signal source is not required. Further, the built-in test signal source creates a test signal by using signals from a VCO and an oscillator, that are used for creating a local oscillation signal for frequency conversion. Thus, the test can be performed inside the integrated circuit with minimum increase of circuit scale.

Abstract: A high-frequency receiving apparatus includes a phase pull-in circuit controlling an oscillator so as to eliminate a phase difference, a frequency pull-in circuit controlling the oscillator so as to eliminate a frequency difference, a frequency shift circuit shifting an oscillation frequency of the oscillator by a prescribed frequency when the frequency difference is large, and a control signal generation circuit controlling those circuits according to an algorithm selected from a plurality of algorithms corresponding to, for example, a symbol rate. Therefore, a wide range of frequency can rapidly be pulled regardless of the level of the symbol rate.

Abstract: A PLL circuit has (i) a counter which divides a frequency of a VCO output whose frequency has been divided by a frequency divider and (ii) a memory which stores plural patterns of set cycles of the counter. The memory reads out one of the set cycles designated by a selection signal inputted through a serial bus (SB) from an outside of the PLL circuit. The set cycle, read out from the memory, which has a large amount of data, is inputted through a parallel bus (PB) into the counter, so that it hardly takes time to set a cycle for the counter. Further, even when the number of bits of the counter increases, the setting time is not lengthened.

Abstract: The subject invention provides a radio-frequency receiving apparatus including a built-in test signal source for producing a radio-frequency test signal. This structure achieves cost reduction, as well as an increase of the yield, since an expensive test signal source is not required. Further, the built-in test signal source creates a test signal by using signals from a VCO and an oscillator, that are used for creating a local oscillation signal for frequency conversion. Thus, the test can be performed inside the integrated circuit with minimum increase of circuit scale.

Abstract: A high-frequency receiving apparatus includes a phase pull-in circuit controlling an oscillator so as to eliminate a phase difference, a frequency pull-in circuit controlling the oscillator so as to eliminate a frequency difference, a frequency shift circuit shifting an oscillation frequency of the oscillator by a prescribed frequency when the frequency difference is large, and a control signal generation circuit controlling those circuits according to an algorithm selected from a plurality of algorithms corresponding to, for example, a symbol rate. Therefore, a wide range of frequency can rapidly be pulled regardless of the level of the symbol rate.