Abstract: The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.

Abstract: In an image coding apparatus to process a frame image generated by combining a plurality of different images in the side-by-side method as a coding target image, information which specifies an image block in contact with a boundary of the plurality of images is input to the image coding apparatus. A control unit sets a predetermined coding control parameter which reduces or inhibits filtering with a deblocking filter on the image block in contact with the boundary of the plurality of images specified based on the input information.

Abstract: An image coding apparatus which divides an input picture into a plurality of macroblocks and performs a prediction encoding for each macroblock, comprising a unit for calculating flatness based on pixel values contained in a macroblock of interest and determining whether the macroblock of interest is a flat macroblock, a unit for storing determination results for each macroblock, a unit for determining, based on the determination results, whether the macroblock of interest determined to be a flat macroblock belongs to a flat area, a unit for selecting one of the inter-prediction mode and the intra-prediction mode as a prediction mode for an encoding process of the macroblock of interest based on determination results and on cost values of the inter-prediction mode and the intra-prediction mode, and a unit for performing predictive coding according to the selected prediction mode.

Abstract: An image processing apparatus determines a specific color region that includes a specific color, and a non-specific color region around which the specific color regions are present in three directions, i.e., an upper, left, and right directions, in a picture in the non-specific color regions that are not determined as including the specific color as specific regions to be subjected to predetermined image processing.

Abstract: The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.

Abstract: To provide a technique to reduce power consumption when carrying out image processing by processors. For the purpose of this, for example, a means for specifying a two-dimensional source register and destination register is provided in an operand of an instruction, and the processor includes a means which executes calculation using a plurality of source registers in a plurality of cycles and obtains a plurality of destinations. Moreover, in an instruction to obtain a destination using a plurality of source registers and consuming a plurality of cycles, a data rounding processing part is connected to a final stage of a pipeline. With such configurations, the power consumed when reading an instruction memory is reduced by reducing the access frequency to the instruction memory, for example.

Abstract: A semiconductor integrated circuit includes a single instruction multiple data (SIMD) unit conducting a concurrent operation for a plurality of data items, a data buffer connectable to the SIMD unit, and a data transfer control unit for controlling transfer of data for the data buffer thereby, the data transfer control unit controls the transfer of data for a subsequent operation to the buffer in concurrence with the operation of the SIMD unit for the plural data items read from the data buffer and in concurrent with the operation of the SIMD unit, data for a subsequent operation is transferred to the data buffer.