Patents by Inventor Yukiharu Akiyama
Yukiharu Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20010004127Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: ApplicationFiled: January 30, 2001Publication date: June 21, 2001Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Publication number: 20010002730Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: ApplicationFiled: January 22, 2001Publication date: June 7, 2001Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Publication number: 20010003048Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: ApplicationFiled: January 25, 2001Publication date: June 7, 2001Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Publication number: 20010003059Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: ApplicationFiled: January 29, 2001Publication date: June 7, 2001Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Publication number: 20010002724Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: ApplicationFiled: January 29, 2001Publication date: June 7, 2001Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Publication number: 20010002064Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: ApplicationFiled: January 17, 2001Publication date: May 31, 2001Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki
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Publication number: 20010002069Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: ApplicationFiled: January 19, 2001Publication date: May 31, 2001Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 6066531Abstract: A method for manufacturing a semiconductor memory device, including the steps of: forming a plurality of stripes comprising a first floating gate material film and a ion implantation protective film, covering one longitudinal side wall of the stripes with a resist pattern; removing a given width of the other side wall of the first floating gate material film by an isotropic etching in use of the resist pattern as a mask; forming an impurity region of low concentration by implanting impurity ions of a second conductivity type into the semiconductor substrate of the first conductivity type in use of the ion implantation protective film as a mask in a tilted direction after removing the resist pattern; and forming asymmetrical impurity regions on both sides of the stripe like first floating gate material film as viewed in the cross section along the direction perpendicular to the longitudinal direction of the stripes.Type: GrantFiled: June 18, 1998Date of Patent: May 23, 2000Assignee: Sharp Kabushiki KaishaInventors: Yukiharu Akiyama, Takuji Tanigami, Shinichi Sato
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Patent number: 6029523Abstract: To suppress the projection of an O ring when a plurality of O rings fitted onto a pipe are inserted into the respective O ring storage chambers of a cup, first and second O ring storage chambers corresponding to the plurality of O rings are formed in the cup, and the line diameter of an O ring which is inserted later is made larger than the line diameter of the O ring which is first inserted.Type: GrantFiled: December 1, 1998Date of Patent: February 29, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yukiharu Akiyama, Hisato Umemaru
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Patent number: 5943595Abstract: A method of manufacturing a semiconductor device having a triple-well structure, includes the steps of: forming a first well layer of a second conductivity type by implanting, as a first ion implantation, impurity ions of the second conductivity type to a specific depth from the surface of a semiconductor substrate of a first conductivity type and then subjecting the semiconductor substrate to an annealing treatment; forming a second ion-implanted region by implanting, as a second ion implantation, impurity ions of the second conductivity type into an end portion of first well layer with a specific width and at a depth from the surface of the semiconductor substrate to the surface of the first well layer to surround the first well layer; forming a third ion-implanted region by implanting, as a third ion implantation, impurity ions of the first conductivity type into a portion of the semiconductor substrate surrounded by the first well layer and the second ion-implanted region and at depth from the surface ofType: GrantFiled: February 24, 1998Date of Patent: August 24, 1999Assignee: Sharp Kabushiki KaishaInventors: Yukiharu Akiyama, Toshiyuki Matsushima, Shinichi Sato
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Patent number: 5884835Abstract: In a case of ultrasonic bonding of a bonding wire to a metal pad provided on a semiconductor substrate, the vibration amplitude of a tip end of the bonding tool is set to be smaller than the film thickness of the metal pad, and the vibration frequency of the bonding tool is set to be higher than 70 kHz. According physical damage, such as cracks produced in a portion beneath the metal pad, can be prevented.Type: GrantFiled: July 26, 1996Date of Patent: March 23, 1999Assignee: Hitachi, Ltd.Inventors: Ryoichi Kajiwara, Toshiyuki Takahashi, Kazuya Takahashi, Masahiro Koizumi, Hiroshi Watanabe, Yukiharu Akiyama
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Patent number: 5880008Abstract: A method for forming a field oxide film includes the steps of: (i) laminating a gate insulating film, a polysilicon layer and a first silicon nitride film over the entire surface of a semiconductor substrate in this order; (ii) patterning the gate insulating film, the polysilicon layer and the first silicon nitride film to a desired shape; (iii) forming a sidewall spacer of a second silicon nitride film on a side wall of the gate insulating film, the polysilicon layer and the first silicon nitride film; (iv) selectively etching a portion of the semiconductor substrate with the first silicon nitride film and the sidewall spacer used as a mask; and (v) forming a field oxide film on the etched portion of the semiconductor substrate in a self-aligned manner relative to the polysilicon layer. According to the invention, lifting up of the polysilicon layer caused by the bird's beak of the field oxide film coming under the polysilicon layer can be reduced.Type: GrantFiled: October 15, 1996Date of Patent: March 9, 1999Assignee: Sharp Kabushiki KaishaInventors: Yukiharu Akiyama, Shinichi Sato
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Patent number: 5493139Abstract: An Electrically Erasable PROM (E.sup.2 PROM) according to the present invention includes a semiconductor substrate of a first conductivity type having a field oxide formed on a predetermined region of the main surface thereof; a memory section formed on the semiconductor substrate; and a peripheral circuit section formed in the peripheral of the memory section, wherein the peripheral circuit section has a CMOS structure in which an N-channel MOS transistor and a P-channel MOS transistor are connected to each other in a complementary manner; one of the N-channel MOS transistor and the P-channel MOS transistor is a thin film transistor formed on the field oxide and the other is a MOS transistor formed on the semiconductor substrate; and the memory section includes a plurality of non-volatile transistors formed on the semiconductor substrate.Type: GrantFiled: May 24, 1994Date of Patent: February 20, 1996Assignee: Sharp Kabushiki KaishaInventors: Yukiharu Akiyama, Shin-ichi Sato
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Patent number: 5176310Abstract: The present invention relates to a ball bonding technique using an insulated wire in assembling a semiconductor chip in which the ball is formed at the end of an insulated wire by an electrical discharge and the insulation at a portion of the wire to be bonded a predetermined distance from one end of the wire is removed by an electrical discharge.Type: GrantFiled: February 18, 1992Date of Patent: January 5, 1993Assignee: Hitachi, Ltd.Inventors: Yukiharu Akiyama, Yoshio Oshima
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Patent number: 5110032Abstract: The present invention relates to a ball bonding technique using an insulated wire in assembling a semiconductor chip in which the ball is formed at the end of an insulated wire by an electrical discharge and the insulation at a portion of the wire to be bonded a predetermined distance from one end of the wire is removed by an electrical discharge.Type: GrantFiled: April 29, 1991Date of Patent: May 5, 1992Assignee: Hitachi, Ltd.,Inventors: Yukiharu Akiyama, Yoshio Oshima
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Patent number: 5037023Abstract: The present invention relates to a ball bonding technique using an insulated wire in assembling a semiconductor chip in which the ball is formed at the end of an insulated wire by an electrical discharge and the insulation at a portion of the wire to be bonded a predetermined distance from one end of the wire is removed by an electrical discharge.Type: GrantFiled: November 28, 1989Date of Patent: August 6, 1991Assignee: Hitachi, Ltd.Inventors: Yukiharu Akiyama, Yoshio Oshima