Patents by Inventor Yukiharu Ieda

Yukiharu Ieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7228064
    Abstract: The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: June 5, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Wada, Makoto Hirai, Tokuzo Kiyohara, Kosuke Yoshioka, Hideshi Nishida, Yukiharu Ieda
  • Publication number: 20030026487
    Abstract: The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.
    Type: Application
    Filed: August 2, 2002
    Publication date: February 6, 2003
    Inventors: Yoshiyuki Wada, Makoto Hirai, Tokuzo Kiyohara, Kosuke Yoshioka, Hideshi Nishida, Yukiharu Ieda