Abstract: A ROM bit map file indicating placement areas of transistors of a mask ROM is prepared from a layout condition of the transistors in the mask ROM and physical positions of the transistors described in a layout pattern file, a logic simulation is performed by using the ROM bit map file and connection information of the transistors, and the physical positions of the transistors are verified according to a simulation result. Therefore, even though there are a large number of transistors in the mask ROM, the physical positions of the transistors can be reliably verified.

Abstract: A semiconductor circuit logical check apparatus including a unit for extracting information about laser trimming fuse elements based on layout data and logic-circuit diagram data of a semiconductor circuit, a unit for generating a command sequence indicating that some of the laser trimming fuse elements are broken on the basis of the extracted laser trimming fuse element information, a unit for generating error bit memory cell array models from memory cell array models, and a unit for executing, on a semiconductor circuit model, logic simulation on the basis of the command sequence.