Patents by Inventor Yukiharu YOSHIMURA

Yukiharu YOSHIMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8930931
    Abstract: In an information processing apparatus, a first processor executes firmware and data processing instructions, a second processor conducts management of firmware updating and system settings, first and second memories store current and updated firmware, a third memory stores system settings information, and a switch changes connections of the first and second memories under control of the second processor, to connect one of the first and second memories to a bus connected to the first processor and to connect the other to the second processor. During firmware execution by the first processor, the second processor reads the system settings information from the third memory and provides it to the first processor. The first processor reflects firmware data from updated firmware in the second memory in the system settings information and the second processor stores the system settings information in which updated firmware data is reflected into the third memory.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: January 6, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Haramiishi, Yukiharu Yoshimura, Takayuki Abe
  • Patent number: 8726049
    Abstract: Without disposing any dedicated management module, it is possible to monitor sensors of shared sections shared among computer modules. A computer system includes a state machine for monitoring a power state of each computer module and a state of a baseboard management controller of the computer module, shared modules of shared sections shared among the computer modules, and switches corresponding to the shared modules for selecting one of the baseboard management controllers to establish connections between the baseboard management controllers and the shared modules. At occurrence of an abnormality in the power state or the baseboard management controller of any one of the computer modules, the state machine dynamically conducts a switching operation to designate one of the baseboard management controllers to monitor sensors of the shared modules.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: May 13, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Toshiharu Kasahara, Yukiharu Yoshimura, Isao Ohara, Masataka Torizawa
  • Publication number: 20120144223
    Abstract: Without disposing any dedicated management module, it is possible to monitor sensors of shared sections shared among computer modules. A computer system includes a state machine for monitoring a power state of each computer module and a state of a baseboard management controller of the computer module, shared modules of shared sections shared among the computer modules, and switches corresponding to the shared modules for selecting one of the baseboard management controllers to establish connections between the baseboard management controllers and the shared modules. At occurrence of an abnormality in the power state or the baseboard management controller of any one of the computer modules, the state machine dynamically conducts a switching operation to designate one of the baseboard management controllers to monitor sensors of the shared modules.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 7, 2012
    Applicant: HITACHI, LTD.
    Inventors: Toshiharu Kasahara, Yukiharu Yoshimura, Isao Ohara, Masataka Torizawa
  • Publication number: 20110099544
    Abstract: The information processing apparatus includes a first processor to execute firmware and instructions for data processing, a second processor to conduct management of at least firmware updating and system settings, a first memory and a second memory capable of storing current firmware and updated firmware, a third memory to store system settings information, and a switch to change connections of the first memory and the second memory under control of the second processor, to connect one of the first and second memories to a bus connected to the first processor and to connect the other one of these memories to the second processor. During execution of firmware by the first processor, the second processor reads the system settings information from the third memory and provides this information to the first processor.
    Type: Application
    Filed: October 21, 2010
    Publication date: April 28, 2011
    Applicant: HITACHI, LTD.
    Inventors: Hiroaki HARAMIISHI, Yukiharu YOSHIMURA, Takayuki ABE