Patents by Inventor Yukihide Ode
Yukihide Ode has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8922468Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.Type: GrantFiled: January 21, 2014Date of Patent: December 30, 2014Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Mitsuru Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
-
Patent number: 8766900Abstract: There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.Type: GrantFiled: March 14, 2013Date of Patent: July 1, 2014Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Yasuhiro Tanaka, Hironobu Isami, Haruhisa Iida, Hidenori Kikuchi, Yukihide Ode
-
Publication number: 20140132645Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.Type: ApplicationFiled: January 21, 2014Publication date: May 15, 2014Applicants: Panasonic Liquid Crystal Display Co., Ltd., Japan Display Inc.Inventors: Mitsuru GOTO, Hiroshi KATAYANAGI, Yukihide ODE, Yoshiyuki SAITOU, Koichi KOTERA
-
Patent number: 8674923Abstract: There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.Type: GrantFiled: January 7, 2013Date of Patent: March 18, 2014Assignees: Japan Display Inc., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Yasuhiro Tanaka, Hironobu Isami, Haruhisa Iida, Hidenori Kikuchi, Yukihide Ode
-
Patent number: 8633882Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.Type: GrantFiled: April 9, 2012Date of Patent: January 21, 2014Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Mitsuru Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
-
Publication number: 20130222350Abstract: There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.Type: ApplicationFiled: March 14, 2013Publication date: August 29, 2013Applicants: Panasonic Liquid Crystal Display Co., Ltd., Hitachi Displays, Ltd.Inventors: Yasuhiro TANAKA, Hironobu Isami, Haruhisa Iida, Hidenori Kikuchi, Yukihide Ode
-
Publication number: 20130120353Abstract: There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.Type: ApplicationFiled: January 7, 2013Publication date: May 16, 2013Applicants: Panasonic Liquid Crystal Displays Co., Ltd., Hitachi Displays, Ltd.Inventors: Yasuhiro TANAKA, Hironobu Isami, Haruhisa Iida, Hidenori Kikuchi, Yukihide Ode
-
Patent number: 8416178Abstract: There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.Type: GrantFiled: September 23, 2011Date of Patent: April 9, 2013Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Yasuhiro Tanaka, Hironobu Isami, Haruhisa Iida, Hidenori Kikuchi, Yukihide Ode
-
Publication number: 20130033658Abstract: In a liquid crystal display device in which a source board (56) connected to a liquid crystal panel by a flex circuit is mounted onto a rear surface of a lower metal frame (54), disconnection in the flex circuit or at a connection portion thereof is avoided. The source board (56) includes a conductor pattern (110) serving as a ground electrode held in contact with the rear surface of the frame (54). A support member (60) for supporting the circuit board (56) is fixed to the frame (54) and includes a cantilever (62) which extends above the source board (56), for pressing the source board (56) against the frame (54). The cantilever (62) enables displacement of the source board (56) along the rear surface of the frame (54) while maintaining a state in which the conductor pattern (110) is held in contact with the frame (54).Type: ApplicationFiled: August 2, 2012Publication date: February 7, 2013Applicant: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.Inventors: Takashi KATO, Yukihide ODE, Shunichi MATSUMOTO, Masato YANAI, Shimon ITAKURA, Tomohiro MAEYAMA
-
Publication number: 20120194574Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.Type: ApplicationFiled: April 9, 2012Publication date: August 2, 2012Inventors: Mitsuru Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
-
Patent number: 8159437Abstract: A semiconductor integrated circuit includes a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor, and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two frame periods.Type: GrantFiled: July 6, 2011Date of Patent: April 17, 2012Assignees: Hitachi Displays, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Mitsuru Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
-
Patent number: 8159486Abstract: A display device includes a pixel driver circuit. Each of level converter circuits in the pixel driver circuit has an input terminal supplied with a signal swinging between a first voltage and a second voltage lower than the first voltage; a first first-conductivity-type transistor having a gate electrode coupled to the input terminal, and a source region coupled to a reference voltage; a second second-conductivity-type transistor having a gate electrode coupled to a drain region of the first transistor, a source region-coupled to a power supply, and a drain region coupled to an output terminal; one circuit element among a diode, a resistor and a fourth second-conductivity-type transistor, coupled between the gate electrode of the second transistor and the power supply; a third first-conductivity-type transistor having a source region coupled to the input terminal, a drain region coupled to the output terminal, and a gate electrode supplied with a do voltage.Type: GrantFiled: June 30, 2008Date of Patent: April 17, 2012Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Haruhisa Okumura, Yukihide Ode
-
Publication number: 20120050146Abstract: There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes an internal control signal generation circuit generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for delay direction and width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.Type: ApplicationFiled: September 23, 2011Publication date: March 1, 2012Inventors: Yasuhiro Tanaka, Hironobu Isami, Haruhisa Iida, Hidenori Kikuchi, Yukihide Ode
-
Patent number: 8054278Abstract: There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for a delay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.Type: GrantFiled: September 20, 2010Date of Patent: November 8, 2011Assignee: Hitachi Displays, Ltd.Inventors: Yasuhiro Tanaka, Hironobu Isami, Haruhisa Iida, Hidenori Kikuchi, Yukihide Ode
-
Publication number: 20110261092Abstract: A semiconductor integrated circuit includes a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor, and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two frame periods.Type: ApplicationFiled: July 6, 2011Publication date: October 27, 2011Inventors: Mitsuru Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
-
Patent number: 7990355Abstract: A semiconductor integrated circuit includes a first register, a second register, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage, and an amplifier including a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor and a first terminal of the second transistors are connected to a first voltage line, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a second voltage line, a second terminal of the first transistor is connected to a second terminal of the third transistor, and a second terminal of the second transistor is connected to a second terminal of the fourth transistor.Type: GrantFiled: November 3, 2010Date of Patent: August 2, 2011Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Mitsuru Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
-
Publication number: 20110043550Abstract: A semiconductor integrated circuit includes a first register, a second register, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage, and an amplifier including a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor and a first terminal of the second transistors are connected to a first voltage line, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a second voltage line, a second terminal of the first transistor is connected to a second terminal of the third transistor, and a second terminal of the second transistor is connected to a second terminal of the fourth transistor.Type: ApplicationFiled: November 3, 2010Publication date: February 24, 2011Inventors: Mitsuro Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
-
Publication number: 20110007065Abstract: There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for a delay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.Type: ApplicationFiled: September 20, 2010Publication date: January 13, 2011Inventors: Yasuhiro Tanaka, Hironobu Isami, Haruhisa Iida, Hidenori Kikuchi, Yukihide Ode
-
Patent number: 7830347Abstract: A liquid crystal display device includes drain signal lines, gate signal lines, thin film transistors, and a drain driver. The drain driver includes an amplifier circuit having a switching circuit which switches between a first state and a second state, the first state being a state where a first input terminal of the amplifier circuit is coupled to an inverting input terminal and a second input terminal is coupled to a noninverting input terminal, and the second state being a state where the first input terminal is coupled to the noninverting input terminal and the second input terminal is coupled to the inverting input terminal. The amplifier circuit supplies signal voltages to the thin film transistors via the drain signal lines which are gray scale voltages one of plus and minus offset voltages in a first frame and in a second frame.Type: GrantFiled: September 27, 2007Date of Patent: November 9, 2010Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd., Hitachi Ulsi Systems Co., Ltd.Inventors: Mitsuru Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
-
Patent number: 7821487Abstract: There is a need for decreasing a variation in times for writing to TFT elements for pixels in a direction along the extension of a gate line in a liquid crystal display apparatus. A display apparatus includes a display panel having multiple gate lines and multiple drain lines arranged in a matrix and a data driver for outputting a display data signal to each drain line. The data driver includes: an internal control signal generation circuit for generating an internal control signal for setting a timing to output a data signal to a drain line of each block on a block basis by dividing the plurality of drain lines into multiple blocks; and a register circuit for recording a setting for division of the block, a setting for a delay direction and a delay width of a timing to output the data signal, and a setting for rising and falling of an internal control signal.Type: GrantFiled: December 15, 2006Date of Patent: October 26, 2010Assignee: Hitachi Displays, Ltd.Inventors: Yasuhiro Tanaka, Hironobu Isami, Haruhisa Iida, Hidenori Kikuchi, Yukihide Ode