Abstract: A data processing device includes an instruction execution unit that executes a first task, a second task and an interrupt task, a counter that counts an execution time of one of the first task and the interrupt task, a first storage unit that stores a set value to start the counter when the execution unit executes one of the first task and the interrupt task, a second storage unit that stores the set value stored in the first storage unit when the instruction execution unit switches from an execution of the first task to an execution of the second task, and a memory that stores the set value stored in the first storage unit when the instruction unit switches from the execution of the first task to an execution of the interrupt task.

Abstract: A data processing device includes an instruction executing part executing a normal task and a management task scheduling an execution order of the normal task with switching the normal task and the management task, a counter measuring an execution state of the normal task being executed in the instruction executing part, and a state controller controlling the counter based on the normal task being executed in the instruction executing part. The instruction executing part determines whether the normal task to be executed next of a plurality of normal tasks scheduled by the management task is a measurement object or not, and outputs an operation signal notifying the state controller of the determination result. The state controller operates the counter in accordance with the branch operation.

Abstract: A data processing device includes an instruction executing part executing a normal task and a management task scheduling an execution order of the normal task with switching the normal task and the management task, a counter measuring an execution state of the normal task being executed in the instruction executing part, and a state controller controlling the counter based on the normal task being executed in the instruction executing part. The instruction executing part determines whether the normal task to be executed next of a plurality of normal tasks scheduled by the management task is a measurement object or not, and outputs an operation signal notifying the state controller of the determination result. The state controller operates the counter in accordance with the branch operation.

Abstract: A data processing device includes an instruction executing part executing a normal task and a management task scheduling an execution order of the normal task with switching the normal task and the management task, a counter measuring an execution state of the normal task being executed in the instruction executing part, and a state controller controlling the counter based on the normal task being executed in the instruction executing part. The instruction executing part determines whether the normal task to be executed next of a plurality of normal tasks scheduled by the management task is a measurement object or not, and outputs an operation signal notifying the state controller of the determination result. The state controller operates the counter in accordance with the branch operation.

Abstract: A distributed shared memory multiprocessor that includes a first processing element, a first memory which is a local memory of the first processing element, a second processing element connected to the first processing element via a bus, a second memory which is a local memory of the second processing element, a virtual shared memory region, where physical addresses of the first memory and the second memory are associated for one logical address in a logical address space of a shared memory having the first memory and the second memory, and an arbiter which suspends an access of the first processing element, if there is a write access request from the first processing element to the virtual shared memory region, according to a state of a write access request from the second processing element to the virtual shared memory region.

Abstract: A data processing apparatus includes a memory which receives and outputs data with a predetermined data width, an operation circuit which outputs a read command or a write command to access the memory, and an access control circuit which replaces a part of first read data read from the memory with a partial data, and outputs partially replaced data as write data to the memory when receiving the write command and the partial data with a data width smaller than the predetermined data width associated with the write command, from the operation circuit. The access control circuit replaces a part of second read data which has been acquired in response to the read command outputted before, instead of the first read data, with the partial data, and outputs replaced partially data as the write data if the write command has been outputted in connection with a read command outputted before the write command.

Abstract: A data processing device includes a computing circuit that accesses a peripheral device connected to through a internal bus, an internal bus connection circuit that is provided between the computing circuit and the internal bus, and switches an enable and a disable state of an access from the computing circuit to the internal bus, an exception notification controller that outputs an exception occurrence notification signal to the computing circuit based on an error occurred in the peripheral device, and a bus disablement controller that instructs the internal bus connection circuit to disable an access from the computing circuit to the internal bus in accordance with the notification of the exception occurrence notification signal, and instructs the internal bus connection circuit to cancel the disablement of the access in accordance with a start of an exception processing based on the exception occurrence notification signal.

Abstract: A data processing device includes a program execution section to supply an operation direction signal to a peripheral device based on an executed program and execute a branch operation in response to a branch direction signal, and a branch wait operation section to receive the branch direction signal and a peripheral device status notification signal indicating whether an operation performed in the peripheral device is being executed. The branch wait operation section outputs an instruction issue stop signal directing waiting of the branch operation to the program execution section if the branch direction signal is input during a period when the peripheral device status notification signal is active indicating that the operation in the peripheral device is being executed.

Abstract: A distributed shared memory multiprocessor that includes a first processing element, a first memory which is a local memory of the first processing element, a second processing element connected to the first processing element via a bus, a second memory which is a local memory of the second processing element, a virtual shared memory region, where physical addresses of the first memory and the second memory are associated for one logical address in a logical address space of a shared memory having the first memory and the second memory, and an arbiter which suspends an access of the first processing element, if there is a write access request from the first processing element to the virtual shared memory region, according to a state of a write access request from the second processing element to the virtual shared memory region.

Abstract: A data processing apparatus includes a memory which receives and outputs data with a predetermined data width, an operation circuit which outputs a read command or a write command to access the memory, and an access control circuit which replaces a part of first read data read from the memory with a partial data, and outputs partially replaced data as write data to the memory when receiving the write command and the partial data with a data width smaller than the predetermined data width associated with the write command, from the operation circuit. The access control circuit replaces a part of second read data which has been acquired in response to the read command outputted before, instead of the first read data, with the partial data, and outputs replaced partially data as the write data if the write command has been outputted in connection with a read command outputted before the write command.

Abstract: A data processing device includes a computing circuit that accesses a peripheral device connected to through a internal bus, an internal bus connection circuit that is provided between the computing circuit and the internal bus, and switches an enable and a disable state of an access from the computing circuit to the internal bus, an exception notification controller that outputs an exception occurrence notification signal to the computing circuit based on an error occurred in the peripheral device, and a bus disablement controller that instructs the internal bus connection circuit to disable an access from the computing circuit to the internal bus in accordance with the notification of the exception occurrence notification signal, and instructs the internal bus connection circuit to cancel the disablement of the access in accordance with a start of an exception processing based on the exception occurrence notification signal.

Abstract: A data processing device includes an instruction executing part executing a normal task and a management task scheduling an execution order of the normal task with switching the normal task and the management task, a counter measuring an execution state of the normal task being executed in the instruction executing part, and a state controller controlling the counter based on the normal task being executed in the instruction executing part. The instruction executing part determines whether the normal task to be executed next of a plurality of normal tasks scheduled by the management task is a measurement object or not, and outputs an operation signal notifying the state controller of the determination result. The state controller operates the counter in accordance with the branch operation.

Abstract: A data processing device includes a program execution section to supply an operation direction signal to a peripheral device based on an executed program and execute a branch operation in response to a branch direction signal, and a branch wait operation section to receive the branch direction signal and a peripheral device status notification signal indicating whether an operation performed in the peripheral device is being executed. The branch wait operation section outputs an instruction issue stop signal directing waiting of the branch operation to the program execution section if the branch direction signal is input during a period when the peripheral device status notification signal is active indicating that the operation in the peripheral device is being executed.