Patents by Inventor Yukihiko Furasawa

Yukihiko Furasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6262586
    Abstract: It is an object of the present invention to provide an optimal probing mode setting method by which the probing area is set by a prober only within the position, of a semiconductor wafer, in which electrode pads are formed, thereby making the protection of the probes possible. According to the present invention, in an inspection mechanism of a multi-type in which a probe card having one set of measuring channels is moved every plural chips out of a plurality of chips which are formed in a matrix on a wafer in order to carry out the inspection, the probe card is moved successively in a mode in which all the channels of the one set of measuring channels are necessarily located in the positions where the respective chips will be measured, whereby it is prevented that the probe is made enter into a tapered face in the end portion of the semiconductor wafer to be damaged.
    Type: Grant
    Filed: September 9, 1997
    Date of Patent: July 17, 2001
    Assignee: Tokyo Electron Limited
    Inventor: Yukihiko Furasawa