Patents by Inventor Yukihiko Tsukuda

Yukihiko Tsukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Imaging device package, method of manufacturing the imaging device package, and electronic apparatus
    Patent number: 8466531
    Abstract: An imaging device package includes: an imaging device chip; a substrate on which the imaging device chip is mounted; a wire that electrically connects the imaging device chip and the substrate at a peripheral edge of the substrate around the imaging device chip; a supporting body that supports an optical member with respect to the substrate; and a bonding section that bonds the supporting body to the substrate while sealing the wire and a bonding terminal of the wire at the peripheral edge of the substrate.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: June 18, 2013
    Assignee: Sony Corporation
    Inventors: Ryotaro Seo, Tohru Itoh, Yukihiko Tsukuda, Tomoyasu Yamada
  • Multilayer wiring substrate having a castellation structure
    Patent number: 8446002
    Abstract: A multilayer wiring substrate has a through hole that passes from a first surface through to a second surface. The multilayer wiring substrate includes an electrical connection terminal formed in at least one of an inner edge portion which is a periphery of the through hole, an outer edge portion which is an outer periphery of the substrate, and a non-edge portion, on at least one of the first surface and the second surface. The electrical connection terminal has a castellation structure that does not pass through to a surface opposite to a formation surface.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: May 21, 2013
    Assignee: Sony Corporation
    Inventors: Noriko Shibuta, Tohru Terasaki, Tomoyasu Yamada, Nobuo Naito, Yukihiko Tsukuda, Ryu Nonoyama
  • Multilayer wiring substrate having a castellation structure
    Patent number: 8344501
    Abstract: A multilayer wiring substrate has a through hole that passes from a first surface through to a second surface. The multilayer wiring substrate includes an electrical connection terminal formed in at least one of an inner edge portion which is a periphery of the through hole, an outer edge portion which is an outer periphery of the substrate, and a non-edge portion, on at least one of the first surface and the second surface. The electrical connection terminal has a castellation structure that does not pass through to a surface opposite to a formation surface.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: January 1, 2013
    Assignee: Sony Corporation
    Inventors: Noriko Shibuta, Tohru Terasaki, Tomoyasu Yamada, Nobuo Naito, Yukihiko Tsukuda, Ryu Nonoyama
  • Imaging device package, method of manufacturing the imaging device package, and electronic apparatus
    Publication number: 20120104536
    Abstract: An imaging device package includes: an imaging device chip; a substrate on which the imaging device chip is mounted; a wire that electrically connects the imaging device chip and the substrate at a peripheral edge of the substrate around the imaging device chip; a supporting body that supports an optical member with respect to the substrate; and a bonding section that bonds the supporting body to the substrate while sealing the wire and a bonding terminal of the wire at the peripheral edge of the substrate.
    Type: Application
    Filed: October 17, 2011
    Publication date: May 3, 2012
    Applicant: Sony Corporation
    Inventors: Ryotaro Seo, Tohru Itoh, Yukihiko Tsukuda, Tomoyasu Yamada
  • Multilayer wiring substrate, stack structure sensor package, and method of manufacturing stack structure sensor package
    Publication number: 20100244166
    Abstract: A multilayer wiring substrate has a through hole that passes from a first surface through to a second surface. The multilayer wiring substrate includes an electrical connection terminal formed in at least one of an inner edge portion which is a periphery of the through hole, an outer edge portion which is an outer periphery of the substrate, and a non-edge portion, on at least one of the first surface and the second surface. The electrical connection terminal has a castellation structure that does not pass through to a surface opposite to a formation surface.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 30, 2010
    Applicant: Sony Corporation
    Inventors: Noriko Shibuta, Tohru Terasaki, Tomoyasu Yamada, Nobuo Naito, Yukihiko Tsukuda, Ryu Nonoyama