Patents by Inventor Yukihiro IWANAGA

Yukihiro IWANAGA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403538
    Abstract: An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape, a step (IIA) of expanding the dicing tape with the laminate in a cooled state, a step (IIB) of loosening the expanded dicing tape, and a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening the spaces between the chips.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: September 3, 2019
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Yukihiro Iwanaga, Kouji Suzumura, Tatsuya Sakuta
  • Publication number: 20180323097
    Abstract: An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape, a step (IIA) of expanding the dicing tape with the laminate in a cooled state, a step (IIB) of loosening the expanded dicing tape, and a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening the spaces between the chips.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 8, 2018
    Inventors: Yukihiro IWANAGA, Kouji SUZUMURA, Tatsuya SAKUTA
  • Patent number: 10008405
    Abstract: An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape, a step (IIA) of expanding the dicing tape with the laminate in a cooled state, a step (IIB) of loosening the expanded dicing tape, and a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening the spaces between the chips.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: June 26, 2018
    Assignee: HITACHI CHEMICAL COMPANY, LTD
    Inventors: Yukihiro Iwanaga, Kouji Suzumura, Tatsuya Sakuta
  • Publication number: 20170213765
    Abstract: A die bonding/dicing sheet, which can solve the problems of the peeling and the dispersion of an adhesive layer from a pressure sensitive adhesive layer in expanding and further the adhesion thereof to a semiconductor chip, is provided. The die bonding/dicing sheet, which is attached to a support member for mounting a semiconductor element in use, comprising: a peerable first base material; an adhesive layer provided on one surface of the first base material; a pressure sensitive adhesive layer, which covers a whole upper surface of the adhesive layer and has a peripheral part which does not overlap the adhesive layer; and a second base material provided on an upper surface of the pressure sensitive adhesive layer, wherein a plane outer shape of the adhesive layer is larger than a plane outer shape of the support member for mounting the semiconductor element, and a distance between an edge of the adhesive layer and an edge of the support member is 1 mm or more and 12 mm or less.
    Type: Application
    Filed: May 19, 2015
    Publication date: July 27, 2017
    Inventors: Ryouji FURUTANI, Kouji SUZUMURA, Yukihiro IWANAGA, Yuuki NAKAMURA
  • Publication number: 20150348821
    Abstract: An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape, a step (IIA) of expanding the dicing tape with the laminate in a cooled state, a step (IIB) of loosening the expanded dicing tape, and a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening the spaces between the chips.
    Type: Application
    Filed: December 26, 2013
    Publication date: December 3, 2015
    Inventors: Yukihiro IWANAGA, Kouji SUZUMURA, Tatsuya SAKUTA