Abstract: A single-chip microcomputer is constituted by a single-chip microcomputer core, an external bus interface circuit, an external bus, a logic circuit and a bus interface. For asynchronously accessing to an exterior from the single-chip microcomputer core, the external bus interface circuit produces an asynchronous access control signal to the exterior based on an access control signal from the single-chip microcomputer core. The internal bus interconnects the single-chip microcomputer core and the external bus interface circuit, and the logic circuit is asynchronously accessible to and from the single-chip microcomputer core. The bus interface circuit is connected to the internal bus and produces an asynchronous access control signal to the logic circuit based on an access control signal inputted through the internal bus.

Abstract: A serial data transfer apparatus includes a time base counter that counts by a clock signal (CLK). The count value of the time base counter at the point of time when the reception of the serial data (R.times.D) is completed is written into the reception buffer together with the reception data. Accordingly, in the central processing unit, when the reception data (R.times.D) is to be processed, the time difference since the reception serial data (R.times.D) can be detected by reading out the count value of the time base counter written in the reception buffer and by reading out the count value of the time base counter at present from the time base counter. Accordingly, time management of the reception data can be performed.

Abstract: An interrupt controller is so configured that if the priority level is divided into 2.sup.n or less levels, the priority levels are scanned in the order of 2.sup.n .fwdarw.2.sup.n-1 .fwdarw.. . . 2.sup.0, and the priority levels having the same order of priority are scanned on the basis of the default values at only one timing. Therefore, even if interrupt requests having the same priority levels compete with each other, an interrupt request signal having the highest priority level can be detected from the competing interrupt requests with only (n+1) timings.

Abstract: A semiconductor integrated memory circuit includes therein a PROM having a plurality of bit cell groups, each of which includes a set of data bit cells for storing data and a set of check bit cells for storing a set of check bits corresponding to a content of the set of data bit cells for correction of error in the data stored in the set of data bit cells. A check bit input circuit is provided which can ensure that, when data to be programmed into a selected set of data bit cells is the same as a data erased condition of the PROM, a set of check bits having the same value as the data erased condition are held in a corresponding set of check bit cells. Therefore, it is possible to omit the writing of that data and a corresponding check bit set into a set of data bit cells and a corresponding set of check bit cells of the PROM, which are address-designated by a given address.

Abstract: A microcomputer system includes a memory storing various processing data including instruction codes, and a data processor for executing an instruction. The memory includes an address pointer for indicating an address for the memory and supplying the stored address to the memory, and an incrementer for incrementing the address pointer. A latch is coupled to the memory for holding an output of the memory read out in accordance with the address supplied from the address pointer. A bus interface is provided for controlling the address pointer and the incrementer so as to cause a one-time transfer to be performed between the memory and the data processor after an address is supplied from the data processor to the address pointer.

Abstract: A comparator unit for discriminating input data bit groups has a first logical circuit to compare an input data bit group with a reference data bit group and produce a consistent data bit group or an inconsistent data bit group. A second logical circuit responds to a masking data bit group and converts the inconsistent data bit group into the consistent data bit group when the masking data bit group specifies a part of the input data bits where the inconsistency takes place. Therefore, a plurality of predetermined data bit groups are detectable on the basis of the single reference data bit group.

Abstract: A microcomputer includes an instruction execution unit and an internal memory formed on the same chip. A first circuit is provided for setting a memory access cycle for a read/write to the internal memory shorter than that for read/write to an external memory. Further, a second circuit is provided for setting the memory access cycle for the read/write to the internal memory substantially equal to that for the read/write to the external memory. The first and second setting circuits are alternatively and selectively activated.

Abstract: An interruption control apparatus includes registers storing priority data and a circuit producing scanning data in a priority order. The priority data is compared with the scanning data by a scanning operation. If the priority data is equal to the scanning data, a coincidence signal is generated. An interruption request signal from an interruption source is transferred to an interruption processing unit only when the coincidence signal is being generated. Thus, a priority control for a plurality of interruption requests can be performed by using a simple hardware circuit without complex software processing.

Abstract: A memory device provided with an improved control circuit for enabling effective interface with a CPU. The device comprises a memory circuit, a first terminal for receiving a strobe signal for placing the memory circuit in an accessed state, a second terminal for receiving a chain of clock signals, digital counter for counting the clock signals in response to the strobe signal having a plurality of different value of count, output terminals, a circuit for selectively deriving a count signal from one of the count output terminal according to a programmed state, and a ready signal generating circuit for generating a ready signal for indicating the completion of the access operation of the memory circuit in response to the count signal.

Abstract: An improved electronic desk-top calculator provided with a warning function, whereby when data processed by an operator exceed a predetermined value, the operator can recognize it. The calculator comprises a plurality of memory means, a plurality of key means for accessing the memory means, a display means for indicating the accessed memory means, means for judging whether the content of the accessed memory is within a predetermined range and means responsive to the judging means for selectively modulating the display means.