Abstract: A memory device including a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.

Abstract: According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.

Abstract: A storage device includes a first electrode, a second electrode, and a resistance change storage layer between the first and second electrodes. The storage layer is either in a first resistance state or in a second resistance state having a resistance higher than the first resistance state and contains at least two elements selected from a group consisting of germanium, antimony, and tellurium. The storage device further includes an interface layer between the first electrode and the resistance change storage layer. The interface layer contains at least one of the elements of the resistance change storage layer and includes a conductive region and an insulating region.

Abstract: A semiconductor storage device includes a memory cell including a core portion that extends in a first direction above a semiconductor substrate; a variable resistance layer that extends in the first direction and is in contact with the core portion; a semiconductor layer that extends in the first direction and is in contact with the variable resistance layer; a first insulator layer that extends in the first direction and is in contact with the semiconductor layer; and a first voltage applying electrode that extends in a second direction orthogonal to the first direction and is in contact with the first insulator layer. The core portion is a vacuum region, or a region containing inert gas.

Abstract: A storage device includes a resistance change memory element including a first electrode, a second electrode, a resistance change layer between the first and second electrodes, including at least two elements selected from a group consisting of germanium (Ge), antimony (Sb), and tellurium (Te), and having a crystal structure with a c-axis oriented in a first direction from the first electrode toward the second electrode, and a first layer between the first electrode and the resistance change layer and including nitrogen (N) and at least one of silicon (Si) or germanium (Ge).

Abstract: A semiconductor memory device, includes: a stack including a wiring layer and an insulation layer alternately stacked in a first direction; a semiconductor layer including a first region overlapping with the insulation layer in a second direction, and a second region overlapping with the wiring layer in the second direction; an insulation region between the wiring layer and the second region; and a memory region on the opposite side of the second region from the wiring layer. The wiring layer is farther from the first region in the second direction than the insulation layer is. The second region has a part between the insulation layers in the first direction and protruding further toward the wiring layer than the first region in the second direction. The memory region has a face opposite to the second region and closer to the wiring layer in the second direction than the first region is.

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

Abstract: A memory device of an embodiment includes: a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.

Abstract: A pseudo static random access memory including a plurality of memory chips and an information storing device is provided. The memory chips transmit a plurality of read/write data strobe signals to a memory controller by using a same bus. Regardless of whether a self refresh collision occurs in the memory chips, when the memory chips perform a read operation, read latency of the memory chips is set to be a fixed period that self refresh is allowed to be completed. The fixed period is greater than initial latency. The information storing device is configured to store information which defines the fixed period. The read/write data strobe signal indicates whether the self refresh collision occurs in the memory chips, and a level of the read/write data strobe signals is constant during the read latency. A method for operating a pseudo static random access memory is also provided.

Abstract: A pseudo static random access memory including a plurality of memory chips and an information storing device is provided. The memory chips transmit a plurality of read/write data strobe signals to a memory controller by using a same bus. Regardless of whether a self refresh collision occurs in the memory chips, when the memory chips perform a read operation, read latency of the memory chips is set to be a fixed period that self refresh is allowed to be completed. The fixed period is greater than initial latency. The information storing device is configured to store information which defines the fixed period. The read/write data strobe signal indicates whether the self refresh collision occurs in the memory chips, and a level of the read/write data strobe signals is constant during the read latency. A method for operating a pseudo static random access memory is also provided.

Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive portion, an insulating film surrounding a side surface of the first conductive portion, an intermediate layer provided on the first conductive portion and the insulating film, a first film including a first portion provided on the intermediate layer and at least one second portion provided in the intermediate layer and outside an upper edge of the first conductive portion, the first film including, above the first conductive portion, a resistance change portion that has a first resistance state and a second resistance state having resistance higher than resistance in the first resistance state, and a second conductive portion provided at least on the resistance change portion.

Abstract: Provided is a solid preparation showing improved stability of N-(4-(1-(2,6-difluorobenzyl)-5-((dimethylamino)methyl)-3-(6-methoxy-3-pyridazinyl)-2,4-dioxo-1,2,3,4-tetrahydrothieno[2,3-d]pyrimidin-6-yl)phenyl)-N?-methoxyurea and a salt thereof in the solid preparation, and a method of stabilizing the compound in a solid preparation. A tablet containing not less than 25 mass % of the compound; a solid preparation containing (1) the compound, and (2) a fat and oil-like substance having a low melting point, which is selected from polyethylene glycol, glycerol monostearate and triethyl citrate; a method of stabilizing the compound in a tablet, including adding not less than 25 mass % of the compound; and a method of stabilizing the compound, including adding a fat and oil-like substance having a low melting point, which is selected from polyethylene glycol, glycerol monostearate and triethyl citrate to a solid preparation containing the compound.

Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive portion, an insulating film surrounding a side surface of the first conductive portion, an intermediate layer provided on the first conductive portion and the insulating film, a first film including a first portion provided on the intermediate layer and at least one second portion provided in the intermediate layer and outside an upper edge of the first conductive portion, the first film including, above the first conductive portion, a resistance change portion that has a first resistance state and a second resistance state having resistance higher than resistance in the first resistance state, and a second conductive portion provided at least on the resistance change portion.

Abstract: Provided is a solid preparation showing improved stability of N-(4-(1-(2,6-difluorobenzyl)-5-((dimethylamino)methyl)-3-(6-methoxy-3-pyridazinyl)-2,4-dioxo-1,2,3,4-tetrahydrothieno[2,3-d]pyrimidin-6-yl)phenyl)-N?-methoxyurea and a salt thereof in the solid preparation, and a method of stabilizing the compound in a solid preparation. A tablet containing not less than 25 mass % of the compound; a solid preparation containing (1) the compound, and (2) a fat and oil-like substance having a low melting point, which is selected from polyethylene glycol, glycerol monostearate and triethyl citrate; a method of stabilizing the compound in a tablet, including adding not less than 25 mass % of the compound; and a method of stabilizing the compound, including adding a fat and oil-like substance having a low melting point, which is selected from polyethylene glycol, glycerol monostearate and triethyl citrate to a solid preparation containing the compound.

Abstract: A solid dispersion for achieving improved solubility and absorbability of a pharmaceutically active ingredient, which contains (1) an amorphous pharmaceutically active ingredient, (2) one or more substances selected from among methyl cellulose and organic acids and (3) an enteric base material. In cases where methyl cellulose is contained therein, the solid dispersion does not contain any water-soluble polymer other than methyl cellulose.

Abstract: Provided is a solid preparation showing improved stability of N-(4-(1-(2,6-difluorobenzyl)-5-((dimethylamino)methyl)-3-(6-methoxy-3-pyridazinyl)-2,4-dioxo-1,2,3,4-tetrahydrothieno[2,3-d]pyrimidin-6-yl)phenyl)-N?-methoxyurea and a salt thereof in the solid preparation, and a method of stabilizing the compound in a solid preparation. A tablet containing not less than 25 mass % of the compound; a solid preparation containing (1) the compound, and (2) a fat and oil-like substance having a low melting point, which is selected from polyethylene glycol, glycerol monostearate and triethyl citrate; a method of stabilizing the compound in a tablet, including adding not less than 25 mass % of the compound; and a method of stabilizing the compound, including adding a fat and oil-like substance having a low melting point, which is selected from polyethylene glycol, glycerol monostearate and triethyl citrate to a solid preparation containing the compound.

Abstract: According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer including a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first surface, and a second surface; a p-side electrode; an n-side electrode; a first p-side pillar; a first n-side pillar; a first insulating layer; a fluorescer layer; a second insulating layer; a p-side interconnect; and an n-side interconnect. The second insulating layer is provided as one body in at least a portion of an outer side of a side surface of the first insulating layer and at least a portion of an outer side of a side surface of the fluorescer layer.

Abstract: A solid dispersion for achieving improved solubility and absorbability of a pharmaceutically active ingredient, which contains (1) an amorphous pharmaceutically active ingredient, (2) one or more substances selected from among methyl cellulose and organic acids and (3) an enteric base material. In cases where methyl cellulose is contained therein, the solid dispersion does not contain any water-soluble polymer other than methyl cellulose.

Abstract: According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer including a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first surface, and a second surface; a p-side electrode; an n-side electrode; a first p-side pillar; a first n-side pillar; a first insulating layer; a fluorescer layer; a second insulating layer; a p-side interconnect; and an n-side interconnect. The second insulating layer is provided as one body in at least a portion of an outer side of a side surface of the first insulating layer and at least a portion of an outer side of a side surface of the fluorescer layer.

Abstract: According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer having a first layer including an n-type semiconductor, a second layer including a p-type semiconductor, a light emitting layer, a first surface, and a second surface opposite to the first surface; an n-side electrode; a p-side electrode; a third layer; an insulating member; an n-side metal portion; and a p-side metal portion. The insulating member has a lower surface. A height of the lower surface is higher than a height of the first surface. The insulating member covers a periphery of the third layer, and has light reflectivity on at least a surface of a part adjacent to a side surface of the third layer.