Abstract: A configuration information storage section (108) stores configuration information for allowing a reconfigurable module to execute a predetermined function. A CPU (100) configures attached reconfigurable modules (103 to 106) according to the number thereof by referencing the configuration information stored in the configuration information storage section (108).

Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Abstract: An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performing an instruction includes a first instruction set, which includes a flag for specifying predicate (301), and one or more second instruction sets including control specification information (302). A low power operation of each control circuit is performed for each instruction according to the instruction execution control function. Thus, without the necessity for increasing a circuit size or decoding time, it is possible to control the pipeline stage of an instruction decode and a preceding pipeline stage, achieving a low power operation of the microprocessor.

Abstract: A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

Abstract: A semiconductor integrated circuit system has a control target circuit executing a program, a system information monitor unit for outputting system information indicating a state of the control target circuit, a circuit characteristic monitor unit for determining a circuit characteristic of the control target circuit and outputting the circuit characteristic as circuit characteristic information, a malfunction determination unit for determining whether or not the control target circuit is normally operating based on the system information, a reference circuit characteristic holding unit for holding the circuit characteristic information as reference circuit characteristic information when the control target circuit is normally operating, a malfunction factor determination unit for determining a malfunction factor based on the circuit characteristic information and on the reference circuit characteristic information when the control target circuit is not normally operating, and a correction target determinatio

Abstract: A logic circuit comprises: an event generator for detecting a variation in data output from a signal source to generate an event which indicates the variation of the data; a plurality of propagation elements for propagating the event in a chained fashion; and a plurality of evaluation elements for evaluating data received at a first stage from the signal source to propagate a result of the evaluation in a chained fashion. When receiving the event, each of the plurality of evaluation elements evaluates the data input to the evaluation element.

Abstract: A data compressing method comprises first step in which a data is orthogonally transformed so that an orthogonal transform data is generated. A processing step executed subsequent to the first step is divided into a processing step for an alternate-current component of the orthogonal transform data and a processing step for a direct-current component of the orthogonal transform data. The processing step for the direct-current component includes a second step in which an inverse transform equivalent to a decoding process of the orthogonal transform data is executed on the orthogonal transform data.

Abstract: The dynamic circuit includes: a dynamic node; an evaluation circuit for changing the charged state of the dynamic node according to a result of logic evaluation for a plurality of input signals; a control circuit for outputting a control signal of which the logic level changes according to the result of logic evaluation performed by a replica of the evaluation circuit; and an initialization circuit for receiving the control signal from the control circuit and an external control signal, to control start and stop of initialization of the dynamic node according to the control signals.

Abstract: An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performing an instruction includes a first instruction set, which includes a flag for specifying predicate (301), and one or more second instruction sets including control specification information (302). A low power operation of each control circuit is performed for each instruction according to the instruction execution control function. Thus, without the necessity for increasing a circuit size or decoding time, it is possible to control the pipeline stage of an instruction decode and a preceding pipeline stage, achieving a low power operation of the microprocessor.

Abstract: A multiprocessor system capable of responding to various types of processing to improve the processing efficiency of the entire system. Each of a plurality of processors holds information indicating the program control mode, a VLIW mode or a multithread mode, in a program synchronization flag of a program controller. A master processor, responsible for program control of the entire system, notifies an instruction memory section for storing instructions in a program of updated information when the program synchronization flag information is updated.

Abstract: An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performing an instruction includes a first instruction set, which includes a flag for specifying predicate (301), and one or more second instruction sets including control specification information (302). A low power operation of each control circuit is performed for each instruction according to the instruction execution control function. Thus, without the necessity for increasing a circuit size or decoding time, it is possible to control the pipeline stage of an instruction decode and a preceding pipeline stage, achieving a low power operation of the microprocessor.

Abstract: Clock control of a sequential circuit is realized with the assumptions that stop of a clock is impossible due to the specifications, and feedback of the output of a memory element does not exist. To this end, the sequential circuit includes a variation detector for detecting a variation occurred in the content of any of master cells which are memory elements included in a master cell group to output a clock control signal, and a clock pulse generator for receiving the clock control signal to generate a clock pulse and supplying the clock pulse to a slave cell which is a memory element included in a clock domain and whose input is varied when the content of any of the master cells which are memory elements included in the master cell group is varied.

Abstract: A logic circuit comprises: an event generator for detecting a variation in data output from a signal source to generate an event which indicates the variation of the data; a plurality of propagation elements for propagating the event in a chained fashion; and a plurality of evaluation elements for evaluating data received at a first stage from the signal source to propagate a result of the evaluation in a chained fashion. When receiving the event, each of the plurality of evaluation elements evaluates the data input to the evaluation element.

Abstract: A circuit analyzing device according to the present invention comprises a capacitance value extracting unit for extracting a capacitance value of a functional element from design information including layout information of a semiconductor integrated circuit and a capacitance value outputting unit for displaying the functional element in the semiconductor integrated circuit or a functional-element connecting wiring linked to the functional element on a design drawing including the layout information of the semiconductor integrated circuit in a discriminating manner in accordance with the capacitance value of the functional element, or comprises a per-attribute capacitance value operation unit for executing an operation of the capacitance value per attribute based on a functional-element attribute library in which attribute information of the functional element in the semiconductor integrated circuit is stored and the capacitance value of the functional element and a per-attribute capacitance value outputting u

Abstract: An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performing an instruction includes a first instruction set, which includes a flag for specifying predicate (301), and one or more second instruction sets including control specification information (302). A low power operation of each control circuit is performed for each instruction according to the instruction execution control function. Thus, without the necessity for increasing a circuit size or decoding time, it is possible to control the pipeline stage of an instruction decode and a preceding pipeline stage, achieving a low power operation of the microprocessor.

Abstract: Clock control of a sequential circuit is realized with the assumptions that stop of a clock is impossible due to the specifications, and feedback of the output of a memory element does not exist. To this end, the sequential circuit includes a variation detector for detecting a variation occurred in the content of any of master cells which are memory elements included in a master cell group to output a clock control signal, and a clock pulse generator for receiving the clock control signal to generate a clock pulse and supplying the clock pulse to a slave cell which is a memory element included in a clock domain and whose input is varied when the content of any of the master cells which are memory elements included in the master cell group is varied.

Abstract: A compiler apparatus that is capable of generating instruction sequences for causing a processor with parallel processing capability to operate with lower power consumption is a compiler apparatus that translates a source program into a machine language program for the processor including a plurality of execution units which can execute instructions in parallel and a plurality of instruction issue units which issue the instructions executed respectively by the plurality of execution units, and includes: a parser unit operable to parse the source program; an intermediate code conversion unit operable to convert the parsed source program into intermediate codes; an optimization unit operable to optimize the intermediate codes so as to reduce a hamming distance between instructions placed in positions corresponding to the same instruction issue unit in consecutive instruction cycles, without changing dependency between the instructions corresponding to the intermediate codes; and a code generation unit operable

Abstract: A multiprocessor system capable of responding to various types of processing to improve the processing efficiency of the entire system. Each of a plurality of processors holds information indicating the program control mode, a VLIW mode or a multithread mode, in a program synchronization flag of a program controller. A master processor, responsible for program control of the entire system, notifies an instruction memory section for storing instructions in a program of updated information when the program synchronization flag information is updated.

Abstract: A Viterbi decoder is provided in which conventional RAMs or the like is used for a path metric memory and a path selection signal memory, and the number of times the memory is accessed in an ACS operation and a trace-back operation is reduced, thus achieving a reduction in power consumption and an increase in speed of processing operations. In this Viterbi decoder, based on branch metrics calculated from input codes by a branch metric operation section, an add-compare-select (ACS) operation section calculates path metrics of respective states by time-sharing processing. The path metrics sequentially calculated by the ACS operation section are delayed temporarily by a path metric permutation section and are permutated to have different time series from those of the path metrics calculated by the ACS operation section, which then are stored in a path metric memory.