Patents by Inventor Yukihiro Sato
Yukihiro Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11946443Abstract: A bonded body wherein functional base material is attached to object to be bonded. Functional base material and object are bonded with functional base material's end portion covered so operational effect neither lost nor adversely affected by fluid, bonded body has strong bonding property preventing functional base material peeled off due to weather. Peelability allows functional base material repair ease. Functional base material provided on object's curved surface to be bonded to along curved and/or smooth surface of object to be bonded to along smooth surface. Functional base material has peripheral side surface with peripheral distal-most end portion. Peripheral gap part provided between object to be bonded to and functional base material on inside of peripheral distal-most end portion and on side opposing to object to be bonded to. Peripheral gap part filled with holding member extending in laminar fan shape from peripheral side surface along curved and/or smooth surface.Type: GrantFiled: December 4, 2020Date of Patent: April 2, 2024Assignees: ASAHI RUBBER INC., HOKUTAKU CO., LTD.Inventors: Nobuyoshi Watanabe, Hideaki Sato, Masafumi Takeyama, Yukihiro Oryu
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Patent number: 11913800Abstract: Provided is a terminal device and the like that can switch a mode of operation as a terminal device in relation to an on-board device to which the terminal device is attached. A terminal device T that is attached to an attachment target device M and that communicates with the attachment target device M comprises a switching means 1 that switches a mode of operation of the terminal device T on the basis of a state of attachment to the attachment target device M and a state of communication with the attachment target device M.Type: GrantFiled: November 17, 2020Date of Patent: February 27, 2024Assignee: PIONEER CORPORATIONInventors: Yukihiro Sato, Hirotatsu Hiruta
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Publication number: 20230003541Abstract: Provided is a terminal device and the like that can switch a mode of operation as a terminal device in relation to an on-board device to which the terminal device is attached. A terminal device T that is attached to an attachment target device M and that communicates with the attachment target device M comprises a switching means 1 that switches a mode of operation of the terminal device T on the basis of a state of attachment to the attachment target device M and a state of communication with the attachment target device M.Type: ApplicationFiled: November 17, 2020Publication date: January 5, 2023Inventors: Yukihiro SATO, Hirotatsu HIRUTA
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Patent number: 11444010Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.Type: GrantFiled: October 1, 2020Date of Patent: September 13, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazunori Hasegawa, Yuichi Yato, Hiroyuki Nakamura, Yukihiro Sato, Hiroya Shimoyama
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Publication number: 20210118781Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.Type: ApplicationFiled: October 1, 2020Publication date: April 22, 2021Inventors: Kazunori HASEGAWA, Yuichi YATO, Hiroyuki NAKAMURA, Yukihiro SATO, Hiroya SHIMOYAMA
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Publication number: 20210038763Abstract: Provided is a collagen sponge which has compressive strength (stress) equivalent to that of a tissue into which the collagen sponge is to be implanted, has no unevenness in structure and stress, and has a pore structure for allowing cells to infiltrate thereinto. The collagen sponge is obtained by subjecting a collagen dispersion, a collagen solution, or a mixture thereof having a collagen concentration of 50 mg/ml or more to freeze-drying and insolubilization treatment thereafter. The collagen sponge thus obtained has a stress of from 10 kPa to 30 kPa when loaded with 10% strain, has in its surface and inside a pore structure having a mean pore diameter ranging from 50 ?m to 400 ?m, and has a pore diameter standard deviation equal to or less than 80% of the mean pore diameter.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Applicants: OSAKA UNIVERSITY, KOKEN CO., LTDInventors: Ken NAKATA, Yukihiro SATO, Daisuke IKEDA, Ichiro FUJIMOTO
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Patent number: 10777490Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.Type: GrantFiled: November 15, 2019Date of Patent: September 15, 2020Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Toshinori Kiyohara
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Publication number: 20200091046Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.Type: ApplicationFiled: November 15, 2019Publication date: March 19, 2020Inventors: Yukihiro Sato, Toshinori Kiyohara
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Publication number: 20200072345Abstract: A gearshift lever device includes: a main body case fixed on a body of a vehicle; and a gearshift lever supported by the main body case in a shiftable manner. The gearshift lever includes a tubular lever pipe and a lever holder having an insertion hole through which the lever pipe is inserted. The lever pipe includes a lever pipe upper portion forming an upper side of the lever pipe and a lever pipe lower portion forming a lower side of the lever pipe. A section modulus of the lever pipe lower portion is greater than that of the lever pipe upper portion. A shape of the lever pipe is changed in a part below an upper end of the main body case and above an upper end of the lever holder such that the lever pipe upper portion and the lever pipe lower portion have different shapes.Type: ApplicationFiled: August 14, 2019Publication date: March 5, 2020Inventors: Akio MATSUMOTO, Tomohiro TAKAHIRO, Katsushi KUBOTA, Yukihiro SATO, Takumi HAKAMATA
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Publication number: 20200072343Abstract: A gearshift lever device includes: a gearshift lever including an operation portion (knob) formed on an upper end portion and a shaft support portion formed on a lower end portion; and a select lever including a holding portion that holds the shaft support portion of the gearshift lever. The select lever further includes a pair of shift direction side wall portions which are disposed across the holding portion with a distance from each other in a shift direction of the gearshift lever, and engage portions which are disposed on the shift direction side wall portions and are to be engaged with the gearshift lever.Type: ApplicationFiled: August 29, 2019Publication date: March 5, 2020Inventors: Akio MATSUMOTO, Tomohiro TAKAHIRA, Katsushi KUBOTA, Yukihiro SATO, Takumi HAKAMATA
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Patent number: 10515877Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.Type: GrantFiled: March 23, 2018Date of Patent: December 24, 2019Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Toshinori Kiyohara
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Patent number: 10236274Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.Type: GrantFiled: May 31, 2017Date of Patent: March 19, 2019Assignee: Renesas Electronics CorporationInventors: Yukihiro Sato, Katsuhiko Funatsu, Takamitsu Kanazawa, Masahiro Koido, Hiroyoshi Taya
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Patent number: 10141248Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.Type: GrantFiled: December 20, 2016Date of Patent: November 27, 2018Assignee: Renesas Electronics CorporationInventors: Akira Muto, Koji Bando, Yukihiro Sato, Kazuhiro Mitamura
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Publication number: 20180315684Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.Type: ApplicationFiled: March 23, 2018Publication date: November 1, 2018Inventors: Yukihiro SATO, Toshinori KIYOHARA
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Patent number: 10049968Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.Type: GrantFiled: December 29, 2017Date of Patent: August 14, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro Sato, Akira Muto, Ryo Kanda, Takamitsu Kanazawa
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Publication number: 20180122727Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Yukihiro SATO, Akira MUTO, Ryo KANDA, Takamitsu KANAZAWA
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Patent number: 9887151Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.Type: GrantFiled: June 6, 2016Date of Patent: February 6, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro Sato, Akira Muto, Ryo Kanda, Takamitsu Kanazawa
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Publication number: 20170308448Abstract: A terminal apparatus includes a memory that has a program area divided in a plurality of blocks, each blocks being set write protection, and a processor coupled to the memory and configured to set a priority level of stored data to each blocks of the memory, respectively, change the priority level to a lower level in accordance with a failure of an internal of the terminal apparatus when the failure is detected, release the write protection in accordance with the changed priority level, and write data that has a possibility of elimination, to the block whose write protection has released, in accordance with the failure.Type: ApplicationFiled: March 25, 2017Publication date: October 26, 2017Applicant: FUJITSU LIMITEDInventor: Yukihiro SATO
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Publication number: 20170263587Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.Type: ApplicationFiled: May 31, 2017Publication date: September 14, 2017Inventors: Yukihiro SATO, Katsuhiko FUNATSU, Takamitsu KANAZAWA, Masahiro KOIDO, Hiroyoshi TAYA
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Patent number: 9704844Abstract: To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).Type: GrantFiled: April 19, 2016Date of Patent: July 11, 2017Assignee: Renesas Electronics CorporationInventors: Katsuhiko Funatsu, Tomoaki Uno, Toru Ueguri, Yukihiro Sato