Abstract: A stabilizer device includes a stabilizer extending in a width direction of a vehicle, and a bush unit. The bush unit includes a bracket formed of metal, and a rubber bush. The rubber bush is formed of a plurality of bush pieces, and is fixed to the stabilizer by an adhesion layer. The adhesion layer is constituted of an adhesion member including an adhesive applied to inner surfaces of the bush pieces. A bonding display portion formed of a part of the adhesion member is provided at a corner on an end face of the bush piece.

Abstract: A stabilizer device includes a stabilizer extending in a width direction of a vehicle, and a bush unit. The bush unit includes a bracket formed of metal, and a rubber bush. The rubber bush is formed of a plurality of bush pieces, and is fixed to the stabilizer by an adhesion layer. The adhesion layer is constituted of an adhesion member including an adhesive applied to inner surfaces of the bush pieces. A bonding display portion formed of a part of the adhesion member is provided at a corner on an end face of the bush piece.

Abstract: A calibration method in which secular change in sensor output values obtained at calibration times is estimated and the next calibration date can be determined at an appropriate interval and a zirconia-type oxygen analyzer using the above calibration method is achieved. The present invention is characterized by the fact that, in a calibration method in which a standard sample having a known value is measured and the output value of a measuring instrument corresponding to a sensor output value at the time of measurement is calibrated, the sensor output value obtained in implemented calibrating operations is stored in succession as the data for calibration history and the state of secular change in said sensor output value is estimated based on the stored past data for calibration history to determine the next calibration date.

Abstract: It is intended to realize a multi-channel measurement system and a power supply method for the system, the system being capable of performing maintenance of each of channel units and detectors without interrupting a power supply to the overall system. The multi-channel measurement system having a plurality of channel units each of which has a detector and performs measurement operation using a detection output from the detector and a power unit which supplies power to the channel units is characterized by a plurality of sub-switches respectively provided for the channel units, each of the sub-switches interrupting the power supply to the relevant channel unit, and a control unit for outputting a result of arithmetic processing of measurement outputs from the channel units and controlling the interruptions by the sub-switches.

Abstract: A calibration method in which secular change in sensor output values obtained at calibration times is estimated and the next calibration date can be determined at an appropriate interval and a zirconia-type oxygen analyzer using the above calibration method is achieved. The present invention is characterized by the fact that, in a calibration method in which a standard sample having a known value is measured and the output value of a measuring instrument corresponding to a sensor output value at the time of measurement is calibrated, the sensor output value obtained in implemented calibrating operations is stored in succession as the data for calibration history and the state of secular change in said sensor output value is estimated based on the stored past data for calibration history to determine the next calibration date.

Abstract: In order to share a device among a plurality of hosts, a switching section is adapted to select one of the hosts by switching and connect it to the device by a serial interface. The switching section can be controlled from the particular host through at least an interface cable. When the switching section switches the host to be connected with the device, power continues to be supplied to the device. Further, a connection recognition protocol to be transmitted from the device when beginning to supply power to the device is transmitted from the switching section. In this way, a quick switching operation free of protocol contradictions is made possible without causing any hardware resetting of the device.

Abstract: A page table on a main storage contains a correspondence between guest virtual address and a host real address, and a TLB in a processor holds said correspondence calculated by a previous address translation. A PTBR holds a real address of a page table. When a processor detects a TLB purge, the processor starts a host when detecting a TLB purge. The host examines a virtual space change processing executed by the guest, and stores a correspondence between a new guest virtual address and a new host real address in the page table.

Abstract: The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. Apparatus for preventing execution of a transaction such as storage access from obstruction by bus competition with low-speed IO access. The invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion unit for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage for storing access data up to a predetermined amount when the access destination is a predetermined module.

Abstract: The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency.

Abstract: The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. The present invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion means for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage means for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to give a bus occupation right to the bus master.

Abstract: A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address.

Abstract: A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address.

Abstract: In order to share a device among a plurality of hosts, a switching section is adapted to select one of the hosts by switching and connect it to the device by a serial interface. The switching section can be controlled from the particular host through at least an interface cable. When the switching section switches the host to be connected with the device, power continues to be supplied to the device. Further, a connection recognition protocol to be transmitted from the device when beginning to supply power to the device is transmitted from the switching section. In this way, a quick switching operation free of protocol contradictions is made possible without causing any hardware resetting of the device.

Abstract: In order to share a device among a plurality of hosts, a switching section is adapted to select one of the hosts by switching and connect it to the device by a serial interface. The switching section can be controlled from the particular host through at least an interface cable. When the switching section switches the host to be connected with the device, power continues to be supplied to the device. Further, a connection recognition protocol to be transmitted from the device when beginning to supply power to the device is transmitted from the switching section. In this way, a quick switching operation free of protocol contradictions is made possible without causing any hardware resetting of the device.

Abstract: A bus system has a bus constructed of a plurality of signal lines for transmission of signals, first and second terminating resistors provided at both ends of the respective signal lines, first, second and third modules coupled to the bus between the first and second terminating resistors and being each operative to transmit a signal through an output circuit of open drain type, first series resistors inserted in the respective signal lines between the first and second modules, and second series resistors inserted in the respective signal lines between the second and third modules.

Abstract: A control method and system when a flash memory is used. as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data.

Abstract: A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data.

Abstract: A sheet measurement and control system that enables easy installation and/or change of types of sensors to be disposed in or about a sensor head that reciprocally scans a sheet along a cross direction transverse to the sheet flow; wherein a plurality of sensors are disposed in or about the sensor head to measure characteristics of the sheet; a plurality of computation devices corresponding to the plurality of sensors are disposed in or about the sensor head to implement computation of the measuring signals from the sensors; a plurality of communication control devices corresponding to the plurality of computation devices are disposed in or about the sensor head for transmitting the processed measuring signals through a general network communication link attached thereto; and man-machine interface connected to the general network communication link monitors data from said communication control devices related to the measured signal and issues instructions to control the sheet manufacturing process.

Abstract: An information processing apparatus includes a plurality of processor boards arranged parallelly on the main board and the DC--DC converters for generating operation voltages for processor devices each disposed between the adjacent processor boards. Further, a metal plate with high thermal conductivity is placed in close contact with an area of each of the processor boards where devices generating a large amount of heat are mounted. Heat dissipating fins are joined to the surface of each of the metal plates so that when the processor boards are mounted on the main board, the heat dissipating fins do not contact the DC--DC converter. The heat dissipating fins and the DC--DC converters are arranged so that they are vertically disposed one over the other with respect to the main board.

Abstract: An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.