Patents by Inventor Yukihiro Takao
Yukihiro Takao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8101496Abstract: A BGA type semiconductor device having high reliability is offered. A pad electrode is formed on a surface of a semiconductor substrate and a glass substrate is bonded to the surface of the semiconductor substrate. A via hole is formed from a back surface of the semiconductor substrate to reach a surface of the pad electrode. An insulation film is formed on an entire back surface of the semiconductor substrate including an inside of the via hole. A cushioning pad is formed on the insulation film. The insulation film is removed from a bottom portion of the via hole by etching. A wiring connected with the pad electrode is formed to extend from the via hole onto the cushioning pad. A conductive terminal is formed on the wiring. Then the semiconductor substrate is separated into a plurality of semiconductor dice.Type: GrantFiled: May 12, 2010Date of Patent: January 24, 2012Assignee: Semiconductor Components Industries, LLCInventor: Yukihiro Takao
-
Patent number: 7981807Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.Type: GrantFiled: March 19, 2008Date of Patent: July 19, 2011Assignee: SANYO Electric Co., Ltd.Inventors: Akira Suzuki, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
-
Patent number: 7919875Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.Type: GrantFiled: December 13, 2007Date of Patent: April 5, 2011Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
-
Publication number: 20100221892Abstract: A BGA type semiconductor device having high reliability is offered. A pad electrode is formed on a surface of a semiconductor substrate and a glass substrate is bonded to the surface of the semiconductor substrate. A via hole is formed from a back surface of the semiconductor substrate to reach a surface of the pad electrode. An insulation film is formed on an entire back surface of the semiconductor substrate including an inside of the via hole. A cushioning pad is formed on the insulation film. The insulation film is removed from a bottom portion of the via hole by etching. A wiring connected with the pad electrode is formed to extend from the via hole onto the cushioning pad. A conductive terminal is formed on the wiring. Then the semiconductor substrate is separated into a plurality of semiconductor dice.Type: ApplicationFiled: May 12, 2010Publication date: September 2, 2010Applicant: SANYO Electric Co., Ltd.Inventor: Yukihiro TAKAO
-
Patent number: 7745931Abstract: A BGA type semiconductor device having high reliability is offered. A pad electrode is formed on a surface of a semiconductor substrate and a glass substrate is bonded to the surface of the semiconductor substrate. A via hole is formed from a back surface of the semiconductor substrate to reach a surface of the pad electrode. An insulation film is formed on an entire back surface of the semiconductor substrate including an inside of the via hole. A cushioning pad is formed on the insulation film. The insulation film is removed from a bottom portion of the via hole by etching. A wiring connected with the pad electrode is formed to extend from the via hole onto the cushioning pad. A conductive terminal is formed on the wiring. Then the semiconductor substrate is separated into a plurality of semiconductor dice.Type: GrantFiled: May 28, 2004Date of Patent: June 29, 2010Assignee: Sanyo Electric Co., Ltd.Inventor: Yukihiro Takao
-
Patent number: 7719102Abstract: A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.Type: GrantFiled: June 4, 2008Date of Patent: May 18, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao
-
Patent number: 7662670Abstract: A glass substrate is bonded through a resin to the top surface of a semiconductor wafer on which a first wiring is formed. A V-shaped groove is formed by notching from the back surface of the wafer. A second wiring connected with the first wiring and extending over the back surface of the wafer is formed. A protection film composed of an organic resin or a photoresist layer to provide protection with an opening is formed on the second wiring by spray coating. A conductive terminal is formed by screen printing using the protection film as a solder mask. A cushioning material may be formed on the back surface of the wafer by spray coating.Type: GrantFiled: July 19, 2006Date of Patent: February 16, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Hiroyuki Shinogi, Akira Suzuki, Yoshinori Seki, Koichi Kuhara, Yukihiro Takao, Hiroshi Yamada
-
Patent number: 7622810Abstract: Disconnection of wiring and deterioration of step coverage are prevented to offer a semiconductor device of high reliability. A pad electrode formed on a silicon die is connected with a re-distribution layer on a back surface of the silicon die. The connection is made through a pillar-shaped conductive path filled in a via hole penetrating the silicon die from the back surface of the silicon die to the pad electrode.Type: GrantFiled: October 14, 2003Date of Patent: November 24, 2009Assignee: Sanyo Electric Co., Ltd.Inventor: Yukihiro Takao
-
Patent number: 7579671Abstract: Disconnection and deterioration in step coverage of wirings are prevented to offer a semiconductor device having higher reliability. A pad electrode is formed on a surface of a silicon die. A via hole penetrating the silicon die is formed from a back surface of the silicon die to the pad electrode. A wiring layer disposed on the back surface of the silicon die runs through the via hole and is electrically connected with the pad electrode. The wiring layer covers a convex portion of silicon on the back surface of the silicon die. A solder ball is formed on the wiring layer on the convex portion of silicon.Type: GrantFiled: May 24, 2004Date of Patent: August 25, 2009Assignee: Sanyo Electric Co., Ltd.Inventor: Yukihiro Takao
-
Patent number: 7575994Abstract: The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate, a first passivation film covering an end portion of the pad electrode and having a first opening on the pad electrode, a plating layer formed on the pad electrode in the first opening, a second passivation film covering an exposed portion of the pad electrode between an end portion of the first passivation film and the plating layer, covering an end portion of the plating layer, and having a second opening on the plating layer, and a conductive terminal formed on the plating layer in the second opening.Type: GrantFiled: June 13, 2006Date of Patent: August 18, 2009Assignee: SANYO Electric Co., Ltd.Inventors: Yuichi Morita, Shinzo Ishibe, Takashi Noma, Hisao Otsuka, Yukihiro Takao, Hiroshi Kanamori
-
Patent number: 7508072Abstract: The invention prevents a pad electrode for external connection of a semiconductor device from being damaged. An electronic circuit, a first pad electrode connected to the electronic circuit, and a second pad electrode connected to the first pad electrode are formed on a semiconductor substrate. A first protection film is formed, covering the first pad electrode and having an opening on the second pad electrode only. A wiring layer is further formed, being connected to the back surface of the first pad electrode through a via hole penetrating the semiconductor substrate and extending from the via hole onto the back surface of the semiconductor substrate.Type: GrantFiled: September 29, 2006Date of Patent: March 24, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Yuichi Morita, Shinzo Ishibe, Takashi Noma, Hisao Otsuka, Yukihiro Takao, Hiroshi Kanamori
-
Publication number: 20080265424Abstract: A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.Type: ApplicationFiled: June 4, 2008Publication date: October 30, 2008Applicant: SANYO Electric Co., Ltd.Inventors: Takashi NOMA, Hiroyuki Shinogi, Yukihiro Takao
-
Publication number: 20080171421Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.Type: ApplicationFiled: March 19, 2008Publication date: July 17, 2008Applicant: SANYO ELECTRIC CO., LTD.Inventors: Akira SUZUKI, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
-
Patent number: 7399683Abstract: A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.Type: GrantFiled: January 14, 2005Date of Patent: July 15, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao
-
Patent number: 7371693Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.Type: GrantFiled: February 24, 2004Date of Patent: May 13, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Akira Suzuki, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
-
Publication number: 20080093708Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.Type: ApplicationFiled: December 13, 2007Publication date: April 24, 2008Applicants: SANYO Electric Co., Ltd., Kanto SANYO Semiconductor Co., Ltd.Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
-
Patent number: 7312107Abstract: A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.Type: GrantFiled: August 4, 2004Date of Patent: December 25, 2007Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
-
Publication number: 20070075425Abstract: The invention prevents a pad electrode for external connection of a semiconductor device from being damaged. An electronic circuit, a first pad electrode connected to the electronic circuit, and a second pad electrode connected to the first pad electrode are formed on a semiconductor substrate. A first protection film is formed, covering the first pad electrode and having an opening on the second pad electrode only. A wiring layer is further formed, being connected to the back surface of the first pad electrode through a via hole penetrating the semiconductor substrate and extending from the via hole onto the back surface of the semiconductor substrate.Type: ApplicationFiled: September 29, 2006Publication date: April 5, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Yuichi Morita, Shinzo Ishibe, Takashi Noma, Hisao Otsuka, Yukihiro Takao, Hiroshi Kanamori
-
Publication number: 20070026639Abstract: A glass substrate is bonded through a resin to the top surface of a semiconductor wafer on which a first wiring is formed. A V-shaped groove is formed by notching from the back surface of the wafer. A second wiring connected with the first wiring and extending over the back surface of the wafer is formed. A protection film composed of an organic resin or a photoresist layer to provide protection with an opening is formed on the second wiring by spray coating. A conductive terminal is formed by screen printing using the protection film as a solder mask. A cushioning material may be formed on the back surface of the wafer by spray coating.Type: ApplicationFiled: July 19, 2006Publication date: February 1, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Takashi Noma, Hiroyuki Shinogi, Akira Suzuki, Yoshinori Seki, Koichi Kuhara, Yukihiro Takao, Hiroshi Yamada
-
Publication number: 20070001302Abstract: The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate, a first passivation film covering an end portion of the pad electrode and having a first opening on the pad electrode, a plating layer formed on the pad electrode in the first opening, a second passivation film covering an exposed portion of the pad electrode between an end portion of the first passivation film and the plating layer, covering an end portion of the plating layer, and having a second opening on the plating layer, and a conductive terminal formed on the plating layer in the second opening.Type: ApplicationFiled: June 13, 2006Publication date: January 4, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Yuichi Morita, Shinzo Ishibe, Takashi Noma, Hisao Otsuka, Yukihiro Takao, Hiroshi Kanamori