Patents by Inventor Yukihiro Utsuno
Yukihiro Utsuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10346068Abstract: A memory system includes a semiconductor storage device including a plurality of blocks of memory cells, each memory cell storing data in a non-volatile state, a controller configured to issue commands to the semiconductor storage device to perform various operations, including a read operation, a write operation, an erase operation, and a dummy operation. The read operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device, and outputs the read data to the controller, and the dummy operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device and does not output the read data to the controller and does not write the data to any of the memory cells of the blocks in the semiconductor storage device.Type: GrantFiled: August 31, 2017Date of Patent: July 9, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroyuki Ishii, Yuji Nagai, Yukihiro Utsuno, Katsuki Matsudera
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Publication number: 20180246660Abstract: A memory system includes a semiconductor storage device including a plurality of blocks of memory cells, each memory cell storing data in a non-volatile state, a controller configured to issue commands to the semiconductor storage device to perform various operations, including a read operation, a write operation, an erase operation, and a dummy operation. The read operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device, and outputs the read data to the controller, and the dummy operation is an operation in which the semiconductor storage device reads data from a memory cell of a block in the semiconductor storage device and does not output the read data to the controller and does not write the data to any of the memory cells of the blocks in the semiconductor storage device.Type: ApplicationFiled: August 31, 2017Publication date: August 30, 2018Inventors: Hiroyuki ISHII, Yuji NAGAI, Yukihiro UTSUNO, Katsuki MATSUDERA
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Patent number: 9515081Abstract: A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the tunnel oxide film and the top oxide film, and smaller than the thickness of the ONO film.Type: GrantFiled: February 23, 2015Date of Patent: December 6, 2016Assignee: Cypress Semiconductor CorporationInventors: Yukio Hayakawa, Yukihiro Utsuno
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Publication number: 20160276356Abstract: A semiconductor memory device of the embodiments includes a first conductivity type semiconductor layer extending in a first direction and including a plurality of projecting regions on the surface thereof, a first insulating film provided on the projecting regions, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control gate provided on the second insulating film.Type: ApplicationFiled: November 19, 2015Publication date: September 22, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Yukihiro UTSUNO
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Publication number: 20160267989Abstract: A nonvolatile semiconductor memory device, includes a memory cell array, and a control circuit configured to control voltage applied to the memory cell array. The memory cell array includes: a plurality of first wiring lines extending in a first direction, a plurality of second wiring lines extending in a second direction intersecting with the first direction, and memory cells arranged in respective intersecting portions between the plurality of first wiring lines and the plurality of second wiring lines. The control circuit changes voltages applied to the plurality of first wiring lines and/or times during which voltages are applied to the plurality of first wiring lines independently in each of predetermined spatial periods.Type: ApplicationFiled: September 10, 2015Publication date: September 15, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuya OGURA, Yukihiro UTSUNO, Kazuhide SUZUKI, Koki UENO, Yasuhiro TOMITA, Makoto NAKASHIMA, Kazuhiko MURAKI, Satoshi AOKI
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Patent number: 9331180Abstract: A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film.Type: GrantFiled: March 5, 2013Date of Patent: May 3, 2016Assignee: Cypress Semiconductor CorporationInventor: Yukihiro Utsuno
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Patent number: 9281383Abstract: A method for fabricating a semiconductor device according to an embodiment, includes forming a silicon (Si) film containing carbon (C) in an upper portion thereof above a semiconductor substrate, performing element isolation of the Si film and the semiconductor substrate to make a width dimension of the Si film narrow in a first region and a width dimension of the Si film wide in a second region, after the element isolation, exposing a side face of the Si film in at least the first region, and diffusing boron (B) into the Si film from the side face of the Si film in the first region.Type: GrantFiled: May 17, 2013Date of Patent: March 8, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Yukihiro Utsuno
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Patent number: 9196495Abstract: A semiconductor device in accordance with one embodiment of the invention can include a semiconductor substrate having a groove, a bit line, a pocket implantation region, a bottom insulating membrane, and a charge accumulation region. The bit line is formed on a side of the groove in the semiconductor substrate and acts as a source and a drain. The pocket implantation region is formed to touch (or contact) the bit line, has a similar conductivity type as the semiconductor substrate, and has a dopant concentration higher than that of the semiconductor substrate. The bottom insulating membrane is formed on and touches (or contacts) a side surface of the groove. The charge accumulation layer is formed on and touches (or contacts) a side surface of the bottom insulating membrane.Type: GrantFiled: June 18, 2012Date of Patent: November 24, 2015Assignee: Cypress Semiconductor CorporationInventor: Yukihiro Utsuno
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Publication number: 20150270278Abstract: A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the tunnel oxide film and the top oxide film, and smaller than the thickness of the ONO film.Type: ApplicationFiled: February 23, 2015Publication date: September 24, 2015Inventors: Yukio HAYAKAWA, Yukihiro UTSUNO
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Patent number: 8994093Abstract: A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the tunnel oxide film and the top oxide film, and smaller than the thickness of the ONO film.Type: GrantFiled: March 14, 2008Date of Patent: March 31, 2015Assignee: Spansion LLCInventors: Yukio Hayakawa, Yukihiro Utsuno
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Publication number: 20140162417Abstract: A method for fabricating a semiconductor device according to an embodiment, includes forming a silicon (Si) film containing carbon (C) in an upper portion thereof above a semiconductor substrate, performing element isolation of the Si film and the semiconductor substrate to make a width dimension of the Si film narrow in a first region and a width dimension of the Si film wide in a second region, after the element isolation, exposing a side face of the Si film in at least the first region, and diffusing boron (B) into the Si film from the side face of the Si film in the first region.Type: ApplicationFiled: May 17, 2013Publication date: June 12, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yukihiro UTSUNO
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Publication number: 20140021529Abstract: A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.Type: ApplicationFiled: October 22, 2012Publication date: January 23, 2014Inventors: Naofumi TAKAHATA, Masahiko HIGASHI, Yukihiro UTSUNO
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Patent number: 8536638Abstract: A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus.Type: GrantFiled: December 14, 2011Date of Patent: September 17, 2013Assignee: Spansion LLCInventors: Yukihiro Utsuno, Namjin Heo
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Patent number: 8537622Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells provided in a matrix and having a charge storage layer, a plurality of word lines provided on the charge storage layer, and an application section. When reading data from a selected memory cell selected from the plurality of memory cells, the application section applies a voltage having an opposite polarity to the voltage applied to a selected word line to non-selected word lines arranged on both adjacent sides of the selected word line.Type: GrantFiled: August 23, 2011Date of Patent: September 17, 2013Assignee: Spansion LLCInventors: Fumiaki Toyama, Yukihiro Utsuno
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Publication number: 20130064024Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells provided in a matrix and having a charge storage layer, a plurality of word lines provided on the charge storage layer, and an application section. When reading data from a selected memory cell selected from the plurality of memory cells, the application section applies a voltage having an opposite polarity to the voltage applied to a selected word line to non-selected word lines arranged on both adjacent sides of the selected word line.Type: ApplicationFiled: August 23, 2011Publication date: March 14, 2013Inventors: Fumiaki Toyama, Yukihiro Utsuno
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Patent number: 8389361Abstract: A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film.Type: GrantFiled: March 22, 2011Date of Patent: March 5, 2013Assignee: Spansion LLCInventor: Yukihiro Utsuno
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Patent number: 8304914Abstract: A method for manufacturing a semiconductor device, the method including: forming a bit line in a semiconductor substrate; forming a plurality of word lines which intersect with the bit line at predetermined intervals on the semiconductor substrate; eliminating a portion of the plurality of word lines; forming an interlayer insulating film on the semiconductor substrate; and forming a metal plug which penetrates through the interlayer insulating film and is coupled to the bit line in a region where the portion of the plurality of word lines was eliminated.Type: GrantFiled: October 26, 2010Date of Patent: November 6, 2012Assignee: Spansion, LLCInventors: Naofumi Takahata, Masahiko Higashi, Yukihiro Utsuno
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Publication number: 20120256245Abstract: A semiconductor device in accordance with one embodiment of the invention can include a semiconductor substrate having a groove, a bit line, a pocket implantation region, a bottom insulating membrane, and a charge accumulation region. The bit line is formed on a side of the groove in the semiconductor substrate and acts as a source and a drain. The pocket implantation region is formed to touch (or contact) the bit line, has a similar conductivity type as the semiconductor substrate, and has a dopant concentration higher than that of the semiconductor substrate. The bottom insulating membrane is formed on and touches (or contacts) a side surface of the groove. The charge accumulation layer is formed on and touches (or contacts) a side surface of the bottom insulating membrane.Type: ApplicationFiled: June 18, 2012Publication date: October 11, 2012Inventor: Yukihiro UTSUNO
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Patent number: 8273627Abstract: A semiconductor device which includes two trenches formed in a semiconductor substrate, a charge storage layer as an insulator formed on each side surface of the trenches, and separated on a bottom surface thereof, and a bit line formed below the bottom surface of the trenches in the semiconductor substrate. A channel region is formed in the semiconductor substrate from a side surface of one of the two trenches to that of the other trench via an upper surface of a protruding portion between those two trenches. A method for manufacturing the semiconductor device is also provided.Type: GrantFiled: December 17, 2008Date of Patent: September 25, 2012Assignee: Spansion LLCInventor: Yukihiro Utsuno
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Patent number: 8202790Abstract: A semiconductor device in accordance with one embodiment of the invention can include a semiconductor substrate having a groove, a bit line, a pocket implantation region, a bottom insulating membrane, and a charge accumulation region. The bit line is formed on a side of the groove in the semiconductor substrate and acts as a source and a drain. The pocket implantation region is formed to touch (or contact) the bit line, has a similar conductivity type as the semiconductor substrate, and has a dopant concentration higher than that of the semiconductor substrate. The bottom insulating membrane is formed on and touches (or contacts) a side surface of the groove. The charge accumulation layer is formed on and touches (or contacts) a side surface of the bottom insulating membrane.Type: GrantFiled: February 5, 2008Date of Patent: June 19, 2012Assignee: Spansion LLCInventor: Yukihiro Utsuno