Abstract: A differential amplifier which does not have an effect of noise resistance deterioration, waveform distortion, and a lower bandwidth while having a wide input range is realized. The differential amplifier does not cause deterioration in a signal quality due to an increase in an input load, and it is not necessary to additionally provide a configuration for generating a reference voltage. The differential amplifier includes a differential amplification circuit and an output circuit for amplifying and outputting a differential output from the differential amplification circuit.

Abstract: A differential amplifier which does not have an effect of noise resistance deterioration, waveform distortion, and a lower bandwidth while having a wide input range is realized. The differential amplifier does not cause deterioration in a signal quality due to an increase in an input load, and it is not necessary to additionally provide a configuration for generating a reference voltage. The differential amplifier includes a differential amplification circuit and an output circuit for amplifying and outputting a differential output from the differential amplification circuit.

Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.

Abstract: A physical quantity distribution detecting apparatus includes a sensor array in which a plurality of unit sensors for sensing physical quantity are two-dimensionally arranged in a matrix; and an analog-to-digital conversion unit that includes a plurality of comparators for comparing an analog signal read from the unit sensor with a reference signal, the analog-to-digital conversion unit converting a digital signal by measuring a period of time or measuring a signal corresponding to the period of time of each comparison output of the plurality of comparators. Each of the plurality of comparators includes at least one capacitor element connected between a signal line and a constant-voltage line.

Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.

Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.

Abstract: An image processing method for obtaining digital data comprising the steps of obtaining a plurality of image signals under a condition of different accumulation periods as an initial value for a counting operation, comparing, by using digital data for a first image signal of the plurality of image signals, an electric signal corresponding to a second image signal of the plurality of image signals with a reference signal, obtaining digital data for the second image signal, performing a counting operation in a mode having the same sign as the sign of digital data for the first image signal between a down-counting mode and an up-counting mode while the comparing step is being performed, and storing a count value.

Abstract: A physical quantity distribution detecting apparatus includes a sensor array in which a plurality of unit sensors for sensing physical quantity are two-dimensionally arranged in a matrix; and an analog-to-digital conversion unit that includes a plurality of comparators for comparing an analog signal read from the unit sensor with a reference signal, the analog-to-digital conversion unit converting a digital signal by measuring a period of time or measuring a signal corresponding to the period of time of each comparison output of the plurality of comparators. Each of the plurality of comparators includes at least one capacitor element connected between a signal line and a constant-voltage line.

Abstract: In a solid-state imaging device meeting color image pickup, which an AD converter is mounted on the same chip, the circuit scale and the number of transmission signal lines are reduced and a reference signal suitable for color image pickup is fed to an AD conversion comparing portion. DA converter circuits for two pixels of a repeat unit of a separation filter in the horizontal row direction in a unit of readout are prepared as a functional portion to generate a reference signal for AD conversion. The DA converter circuits generate the reference signals having a tilt in accordance with a color property and varying from an initial value based on a non-color property such as a black reference and a circuit offset. Each reference signal independently outputted from the DA converter circuits is basically directly transmitted through common signal lines to a voltage comparing portion which corresponds to color filters having a common color property through independent signal lines.

Abstract: A data processing apparatus and method is disclosed for obtaining digital data for a plurality of signals to be processed, comprising. The disclosed process includes comparing, by using digital data for a first signal of the plurality of signals, an electric signal corresponding to a second signal of the plurality of signals with a reference signal; obtaining digital data for the second signal based on the comparing step; performing a counting operation in one of a down-counting mode and an up-counting mode while the comparing step is being performed; storing a first count value; outputting the first count value as computed data at a predetermined time; generating normal data based on one of the plurality of signals to be processed; and outputting the normal data.

Abstract: In a solid-state imaging device with an AD converter mounted on the same chip, to enable an efficient product-sum operation while reducing the size of the circuit scale and the number of transmission signal lines. A pixel signal during an n-row readout period is compared with a reference signal for digitizing this pixel signal, and a counting operation is performed in one of a down-counting mode and an up-counting mode while the comparison processing is being performed, and then, the count value when the comparison processing is finished is stored. Subsequently, by using the n-row counting result as the initial value, a pixel signal during an (n+1)-row readout period is compared with the reference signal for digitizing this pixel signal, and also, the counting operation is performed in one of the down-counting mode and the up-counting mode, and then, the count value when the comparison processing is finished is stored.

Abstract: A physical quantity distribution detecting apparatus includes a sensor array in which a plurality of unit sensors for sensing physical quantity are two-dimensionally arranged in a matrix; and an analog-to-digital conversion unit that includes a plurality of comparators for comparing an analog signal read from the unit sensor with a reference signal, the analog-to-digital conversion unit converting a digital signal by measuring a period of time or measuring a signal corresponding to the period of time of each comparison output of the plurality of comparators. Each of the plurality of comparators includes at least one capacitor element connected between a signal line and a constant-voltage line.

Abstract: There is provided a solid-state image pickup device including: a pixel array portion which includes a plurality of unit pixels each having a photoelectric conversion element and an output transistor for outputting a signal according to charge obtained by photoelectric conversion of the photoelectric conversion element; a comparing portion which compares the signal output from each of the unit pixels with a ramp-shaped reference signal; a measuring portion which starts an operation in synchronization with the supply of the reference signal to the comparing portion, performs the operation until the comparison output of the comparing portion is inverted, and measures a time until the comparison of the comparing portion is finished; and a detecting portion which detects a predetermined image pickup condition and fixes the comparison output of the comparing portion to a state before the comparison starts when the image pickup condition is detected.

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Abstract: A solid-state image pick up device including a pixel array unit having unit pixels arranged in a matrix pattern. Each unit pixel includes a photoelectric converter. Additionally, the solid-state image pick up device has column signal lines that correspond to the respective columns of the matrix pattern, a row scanning means for selectively controlling each unit pixel, and an analog-digital converting unit for converting analog signals output from the unit pixels in a row selectively controlled by the row scanning means. The analog-digital converting unit further includes an asynchronous counter which performs counting in two modes and the asynchronous counter includes a counter processor configured so that when switching between the count modes occurs, a running count value is broken and there is an interval between the count modes and when a mode begins the running count value is reset to the value before the running count value was broken.

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Abstract: The present invention provides a solid-state imaging device including: a pixel array block; a row scanning device; and an analogue-digital conversion device, the analogue-digital conversion device including: a comparing device having a reset device; a counting device that counts a comparison period from initiation to completion of comparison performed by the comparing device; and a changing device that changes a voltage at the other input terminal to a predetermined voltage after a resetting operation performed by the reset device.

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Abstract: In an analog-to-digital conversion method for converting a difference signal component representing a difference between a reference component and a signal component in an analog signal to be processed into digital data, in a first process, a signal corresponding to one of the reference component and the signal component is compared with a reference signal for conversion into the digital data. Concurrently with the comparison, counting is performed in one of a down-count mode and an up-count mode, and a count value at a time of completion of the comparison is held. In a second process, a signal corresponding to the other one of the reference component and the signal component is compared with the reference signal. Concurrently with the comparison, counting is performed in the other one of the down-count mode and the up-count mode, and a count value at a time of completion of the comparison is held.

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.