Patents by Inventor Yukihisa Hitsuda

Yukihisa Hitsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110012146
    Abstract: There is provided a light-emitting device including a second electrode which exhibits a stable behavior in a process for manufacturing a light-emitting device or during an operation of a light-emitting device. A light-emitting device includes a first compound semiconductor layer 11 with an n-type conductivity type, an active layer 12 formed on the first compound semiconductor layer 11 and composed of a compound semiconductor, a second compound semiconductor layer 13 with a p-type conductivity type formed on the active layer 12, a first electrode 15 electrically connected to the first compound semiconductor layer 11, and a second electrode 14 formed on the second compound semiconductor layer 13, wherein the second electrode 14 is composed of a titanium oxide, has an electron concentration of 4×1021/cm3 or more, and reflects light emitted from the active layer.
    Type: Application
    Filed: March 13, 2009
    Publication date: January 20, 2011
    Applicant: SONY CORPORATION
    Inventors: Yukihisa Hitsuda, Tatsuo Ohashi
  • Patent number: 7189665
    Abstract: A manufacturing method for a crystalline semiconductor material including a plurality of semiconductor crystal grains is provided. The manufacturing method includes forming an amorphous or polycrystalline semiconductor layer on a substrate having a flat surface; forming a plurality of projections each having a side wall surface substantially perpendicular to the flat surface of the substrate, a height set in the range of about 1 nm to less than or equal to about ¼ of the thickness of the semiconductor layer, and a lateral dimension set in the range of about 3 ?m to about 18 ?m in a direction parallel to the flat surface of the substrate; and heating the semiconductor layer a number of times by using a pulsed laser thereby forming the crystalline semiconductor material including the crystal grains each having a specific plane orientation with respect to a direction perpendicular to the flat surface of the substrate so that the crystal grains respectively correspond to the projections.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: March 13, 2007
    Assignee: Sony Corporation
    Inventors: Kazushi Nakano, Yukihisa Hitsuda, Toshio Fujino, Michinori Shiomi, Junichi Sato
  • Publication number: 20060084246
    Abstract: A manufacturing method for a crystalline semiconductor material including a plurality of semiconductor crystal grains is provided. The manufacturing method includes forming an amorphous or polycrystalline semiconductor layer on a substrate having a flat surface; forming a plurality of projections each having a side wall surface substantially perpendicular to the flat surface of the substrate, a height set in the range of about 1 nm to less than or equal to about ¼ of the thickness of the semiconductor layer, and a lateral dimension set in the range of about 3 ?m to about 18 ?m in a direction parallel to the flat surface of the substrate; and heating the semiconductor layer a number of times by using a pulsed laser thereby forming the crystalline semiconductor material including the crystal grains each having a specific plane orientation with respect to a direction perpendicular to the flat surface of the substrate so that the crystal grains respectively correspond to the projections.
    Type: Application
    Filed: December 2, 2005
    Publication date: April 20, 2006
    Inventors: Kazushi Nakano, Yukihisa Hitsuda, Toshio Fujino, Michinori Shiomi, Junichi Sato
  • Patent number: 6972246
    Abstract: A manufacturing method for a crystalline semiconductor material including a plurality of semiconductor crystal grains is provided. The manufacturing method includes forming an amorphous or polycrystalline semiconductor layer on a substrate having a flat surface; forming a plurality of projections each having a side wall surface substantially perpendicular to the flat surface of the substrate, a height set in the range of about 1 nm to less than or equal to about ¼ of the thickness of the semiconductor layer, and a lateral dimension set in the range of about 3 ?m to about 18 ?m in a direction parallel to the flat surface of the substrate; and heating the semiconductor layer a number of times by using a pulsed laser thereby forming the crystalline semiconductor material including the crystal grains each having a specific plane orientation with respect to a direction perpendicular to the flat surface of the substrate so that the crystal grains respectively correspond to the projections.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: December 6, 2005
    Assignee: Sony Corporation
    Inventors: Kazushi Nakano, Yukihisa Hitsuda, Toshio Fujino, Michinori Shiomi, Junichi Sato
  • Publication number: 20050006646
    Abstract: A manufacturing method for a crystalline semiconductor material including a plurality of semiconductor crystal grains is provided. The manufacturing method includes forming an amorphous or polycrystalline semiconductor layer on a substrate having a flat surface; forming a plurality of projections each having a side wall surface substantially perpendicular to the flat surface of the substrate, a height set in the range of about 1 nm to less than or equal to about ¼ of the thickness of the semiconductor layer, and a lateral dimension set in the range of about 3 ?m to about 18 ?m in a direction parallel to the flat surface of the substrate; and heating the semiconductor layer a number of times by using a pulsed laser thereby forming the crystalline semiconductor material including the crystal grains each having a specific plane orientation with respect to a direction perpendicular to the flat surface of the substrate so that the crystal grains respectively correspond to the projections.
    Type: Application
    Filed: May 28, 2004
    Publication date: January 13, 2005
    Inventors: Kazushi Nakano, Yukihisa Hitsuda, Toshio Fujino, Michinori Shiomi, Junichi Sato