Abstract: Detecting a touch on a touch sensor is performed using a microcomputer without requiring a large-resistance resistor. A capacitive electrode of the touch sensor is coupled to an external terminal of the microcomputer. The microcomputer comprises a current source circuit (e.g., constant current circuit) and an interface section which are coupled to the external terminal, a counter circuit coupled to the interface section, and a central processing unit (CPU). The CPU, after initializing accumulated charge on the touch sensor by an output circuit of the interface section, integrates charge onto the touch sensor with an output current of the current source circuit, acquires a time interval counted by the counter circuit until a signal obtained from an input circuit of the interface section inverts, and discerns whether or not the touch sensor has been touched, depending on the time count value.

Abstract: A debug instruction program is executed to enable a latch contents setting register to select the address of a specified part of a memory to be monitored. The selected address is given to a latch timing controller 18, and the internal state of the specified part of memory is supplied to a display contents latch unit according to information from an address bus and a bus timing control signal. The display contents latch unit latches the internal state and supplies it to a display device so that the internal state of memory can be identified and debugged.

Abstract: A microcomputer includes addressable functional blocks and an internal state latch coupling an A/D converter to an internal bus. A programmable selector is coupled to the address bus and controls the latch to latch data when a selected address is generated on the address bus to that the latched data is provided as an external analog signal for monitoring.

Abstract: A slave mode/master mode switching flag, a switch 19, and a start bit 0/1 generator 20 are provided in a two-way communication device 1 incorporated in a microcomputer. In a slave mode, data transmission and reception are synchronized with a start bit over a communication line, and the communication device does not output a start bit for transmission. In a master mode, data transmission is synchronized with a start bit outputted from the communication device, and data reception is synchronized with a start bit over the communication line. The communication device outputs a start bit for communication data. Two-wire two-way serial communication is effected by combining microcomputers set at a master mode. Single-wire two-way serial communication is effected by combining a microcomputer set at a master mode and another microcomputer set at a slave mode.

Abstract: A pulse generating circuit equipped with a data register (17) in which there are stored data to designate output terminals (14a to 14m) which generate output pulses and data to define the output states of the output terminals (14a to 14m). Also included in the pulse generating circuit is a decoder (16) for decoding the contents of the data register (17) to output the decoding result to a port latch (15) having the output terminals (14a to 14m), so that one selected from the output terminals (14a to 14m) generates the output pulse.