Abstract: An information processing apparatus including a mode setting circuit which comprises a setting means for setting a test operate mode at power on, a means for checking a read-data from an input port in the test operate mode, means of maintaining the test operate mode in cases where the read-data is in agreement with a reference data and switching the test operate mode to a user operate mode in cases where the read-data is not in agreement with a reference data.

Abstract: According to the frequency multiplier of the present invention, an output clock signal of multiplied frequency is emitted from an exclusive NOR circuit which enters an input clock signal and a signal obtained by delaying the input clock signal via a first delay circuit. To the first delay circuit, second and third delay circuits are sucessively cascaded to delay the input clock signal. A circuit which comprises two flip-flops is supplied with the input clock signal and the output of the third delay circuit to emit a set signal when the rise in output of the third delayed circuit becomes faster than the fall of the input clock signal due to change in the delay time caused by the external conditions.

Abstract: An oscillation inducing circuit includes a power-on circuit connected to a power supply of V.sub.DD, a plurality of transfer gates, and a capacitor. The power-on circuit (1) supplies a control signal having a first level to the transfer gates so that a capacitor is charged in a first polarity direction to an instantaneous level of the increasing power supply voltage, and (2) supplies a control signal having a second level so that the capacitor is charged in a second polarity direction, opposite to the first direction, to a voltage equal to an addition of the previously charged voltage and the present instantaneous power supply voltage. Together, these two charges produce a relatively high voltage for initializing the circuit and starting an oscillator.