Abstract: A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.

Abstract: A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to output read data; and a data transfer circuit configured to sequentially transfer read data in units of pages latched in the buffer to the output circuit, wherein the data transfer circuit includes: at least one layer of a scan register train including a plurality of serially connected scan registers having a register and a multiplexer connected to each other to operate for each of clocks, wherein an output of the multiplexer is connected to an input of a register, and an input of a multiplexer is connected to an output of a register in a next previous stage.

Abstract: A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling data access, wherein the control part accesses data by a first processing of reading out a plurality of words of data from memory cells of a word line and a plate line selected according to a row address and storing it in the sense amplifiers, a second processing of selecting sense amplifiers from the column address and inputting/outputting data with the outside, and a third processing of writing back the data of the sense amplifiers into the memory cells, with data being continuously input or output and transferred by repeatedly executing the second processing using the column address generated in the internal counter for a group of words read out to the sense amplifiers at the first processing, and a file storage device and a computer system util

Abstract: A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to output read data; and a data transfer circuit configured to sequentially transfer read data in units of pages latched in the buffer to the output circuit, wherein the data transfer circuit includes: at least one layer of a scan register train including a plurality of serially connected scan registers having a register and a multiplexer connected to each other to operate for each of clocks, wherein an output of the multiplexer is connected to an input of a register, and an input of a multiplexer is connected to an output of a register in a next previous stage.

Abstract: In a data reading method, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell, reference signal generating data corresponding to a high level side is written to the memory cell, a second reading pulse is applied to the memory cell to generate a second signal corresponding to the reference signal generating data, and a reference signal is generated on the basis of the second signal. Then the first signal and the reference signal are compared with each other to determine the stored data stored in the memory cell. In data writing, high-level data is written to the memory cell without using a bit line.

Abstract: A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling data access, wherein the control part accesses data by a first processing of reading out a plurality of words of data from memory cells of a word line and a plate line selected according to a row address and storing it in the sense amplifiers, a second processing of selecting sense amplifiers from the column address and inputting/outputting data with the outside, and a third processing of writing back the data of the sense amplifiers into the memory cells, data being continuously input or output and transferred by repeatedly executing the second processsing using the column address generated in the internal counter for a group of words read out to the sense amplifiers at the first processing,and a file storage device and a computer system utilizing

Abstract: In a data reading method, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell, reference signal generating data corresponding to a high level side is written to the memory cell, a second reading pulse is applied to the memory cell to generate a second signal corresponding to the reference signal generating data, and a reference signal is generated on the basis of the second signal. Then the first signal and the reference signal are compared with each other to determine the stored data stored in the memory cell. In data writing, high-level data is first written to the memory cell without using a bit line.

Abstract: In a data reading method according to the present invention, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell. Next, reference signal generating data corresponding to a high level side is written to the memory cell. Next, a second reading pulse is applied to the memory cell to generate a second signal corresponding to the reference signal generating data. Next, a reference signal is generated on the basis of the second signal. Then the first signal and the reference signal are compared with each other to determine the stored data stored in the memory cell. In data writing, high-level data is first written to the memory cell without using a bit line. A high-level or low-level signal corresponding to data to be written is applied to the bit line in advance. When a low-level signal is applied to the bit line, low-level data is written from the bit line to the memory cell.

Abstract: A D/A converter capable of temporally controlling output of analog data during D/A conversion is provided. The digital to analog converter includes a ferroelectric non-volatile semiconductor memory. The ferroelectric non-volatile semiconductor memory includes a data line, a memory unit which has M memory cells, and M plate lines. Each of the memory cells includes a first electrode, a ferroelectric layer and a second electrode. The first electrode of the memory cells is shared in the memory unit and is connected to the data line. The second electrode of the mth memory cell is connected to the mth plate line. And the area of the ferroelectric layer of the memory cells varies among the memory cells.

Abstract: A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.

Abstract: In a data reading method according to the present invention, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell. Next, reference signal generating data corresponding to a high level side is written to the memory cell. Next, a second reading pulse is applied to the memory cell to generate a second signal corresponding to the reference signal generating data. Next, a reference signal is generated on the basis of the second signal. Then the first signal and the reference signal are compared with each other to determine the stored data stored in the memory cell. In data writing, high-level data is first written to the memory cell without using a bit line. A high-level or low-level signal corresponding to data to be written is applied to the bit line in advance. When a low-level signal is applied to the bit line, low-level data is written from the bit line to the memory cell.

Abstract: A D/A converter capable of temporally controlling output of analog data during D/A conversion is provided. The digital to analog converter includes a ferroelectric non-volatile semiconductor memory. The ferroelectric non-volatile semiconductor memory includes a data line, a memory unit which has M memory cells, and M plate lines. Each of the memory cells includes a first electrode, a ferroelectric layer and a second electrode. The first electrode of the memory cells is shared in the memory unit and is connected to the data line. The second electrode of the mth memory cell is connected to the mth plate line. And the area of the ferroelectric layer of the memory cells varies among the memory cells.

Abstract: A D/A converter capable of temporally controlling output of analog data during D/A conversion is provided. The digital to analog converter includes a ferroelectric non-volatile semiconductor memory. The ferroelectric non-volatile semiconductor memory includes a data line, a memory unit which has M memory cells, and M plate lines. Each of the memory cells includes a first electrode, a ferroelectric layer and a second electrode. The first electrode of the memory cells is shared in the memory unit and is connected to the data line. The second electrode of the mth memory cell is connected to the mth plate line. And the area of the ferroelectric layer of the memory cells varies among the memory cells.

Abstract: A D/A converter capable of temporally controlling output of analog data during D/A conversion is provided. The digital to analog converter includes a ferroelectric non-volatile semiconductor memory. The ferroelectric non-volatile semiconductor memory includes a data line, a memory unit which has M memory cells, and M plate lines. Each of the memory cells includes a first electrode, a ferroelectric layer and a second electrode. The first electrode of the memory cells is shared in the memory unit and is connected to the data line. The second electrode of the mth memory cell is connected to the mth plate line. And the area of the ferroelectric layer of the memory cells varies among the memory cells.

Abstract: Input MPEG coded image data is input through a buffer to a variable length decoding unit where it is subject to variable length decoding. The quantized DCT coefficients are output to an inverse quantization unit, while the motion vectors are output to a motion compensation prediction unit. The quantized DCT coefficients are inversely quantized at the inverse quantization unit to generate DCT coefficients. The DCT coefficients have values of the items of frequencies higher than the desired frequency limit converted to 0 at the DCT coefficient conversion unit whereby the motion data found at the format conversion unit is added at the adder and the result input as the original image data to the format conversion unit. The pixels are thinned at the format conversion unit to generate a compressed image which is then displayed on a display unit.