Abstract: Various embodiments of the present technology may provide methods and system for an integrated circuit. The system may provide a plurality of integrated circuits (i.e., slave devices) connected to and configured to communicate with a host device. Each integrated circuit may comprise a register storing a common default address. Each integrated circuit may further comprise an interface circuit configured to overwrite the default address of one integrated circuit with a new address while preventing changes to the remaining integrated circuits.

Abstract: Various embodiments of the present technology may provide methods and system for an integrated circuit. The system may provide a plurality of integrated circuits (i.e., slave devices) connected to and configured to communicate with a host device. Each integrated circuit may comprise a register storing a common default address. Each integrated circuit may further comprise an interface circuit configured to overwrite the default address of one integrated circuit with a new address while preventing changes to the remaining integrated circuits.

Abstract: Various embodiments of the present technology may provide methods and system for communication between a host device and slave devices. The system may provide a plurality of integrated circuits (i.e., slave devices) connected to and configured to communicate with a host device (i.e., a master device). Each integrated circuit may provide a register to store a unique slave address, a global slave address, and an order number. The host device may communicate with each slave device individually using the unique slave address and communicate with all slave devices simultaneously using the global slave address and the order number.

Abstract: Various embodiments of the present technology may provide methods and system for an integrated circuit. The system may provide a plurality of integrated circuits (i.e., slave devices) connected to and configured to communicate with a host device. Each integrated circuit may comprise a register storing a common default address. Each integrated circuit may further comprise an interface circuit configured to overwrite the default address of one integrated circuit with a new address while preventing changes to the remaining integrated circuits.

Abstract: A decimation filter in which a coefficient word length of a last-stage FIR filter is shorter than that which attains a necessary attenuation rate, and an interpolation filter in which a coefficient word length of a first-stage FIR filter is the same. The coefficient is arranged such that a region in which attenuation is insufficient is caused intensively around a Nyquist frequency. The attenuation in such a region relative to the first or last-stage FIR filter is enhanced so as to ensure sufficient attenuation, by its preceding or following FIR filter. As a result, sufficient attenuation is maintained in an inhibition region while maintaining a relatively small circuit size.

Abstract: A decimation filter in which a coefficient word length of a last-stage FIR filter is shorter than that which attains a necessary attenuation rate, and an interpolation filter in which a coefficient word length of a first-stage FIR filter is the same. The coefficient is arranged such that a region in which attenuation is insufficient is caused intensively around a Nyquist frequency. The attenuation in such a region relative to the first or last-stage FIR filter is enhanced so as to ensure sufficient attenuation, by its preceding or following FIR filter. As a result, sufficient attenuation is maintained in an inhibition region while maintaining a relatively small circuit size.