Abstract: A tester instruction generation unit generates a tester instruction for terminals of a plurality of devices connected to a tester based on an instruction of a user program and causes an instruction storage unit to store the tester instruction. A transfer mode setting unit sets a transfer mode to either a successive transfer mode or a batch transfer mode, based on the number of tester instructions in the instruction storage unit or an instruction of the user program. A transfer control unit transmits the tester instruction in the instruction storage unit to the tester in accordance with the set transfer mode.

Abstract: A tester instruction generation unit generates a tester instruction for terminals of a plurality of devices connected to a tester based on an instruction of a user program and causes an instruction storage unit to store the tester instruction. A transfer mode setting unit sets a transfer mode to either a successive transfer mode or a batch transfer mode, based on the number of tester instructions in the instruction storage unit or an instruction of the user program. A transfer control unit transmits the tester instruction in the instruction storage unit to the tester in accordance with the set transfer mode.

Abstract: A testing device has plural pin electronics substrates and a control substrate. The control substrate includes a first instruction code memory storing an instruction code, a first program counter incrementing a count in synchronization with a clock, a code analysis circuit analyzing the instruction code read from the first instruction code memory in accordance with a counter value, and a control data output control circuit outputting control data for controlling the pin electronics substrates in accordance with the instruction code. Each pin electronics substrate includes a first pin memory storing pin data, a second program counter incrementing a count in synchronization with the clock, and a pin data output control circuit adjusting, based on control data, the count value of the second program counter and outputting pin data read from the first pin memory, the pin data being dependent on the count value of the second program counter.

Abstract: A tester instruction generation unit generates a tester instruction for terminals of a plurality of devices connected to a tester based on an instruction of a user program and causes an instruction storage unit to store the tester instruction. A transfer mode setting unit sets a transfer mode to either a successive transfer mode or a batch transfer mode, based on the number of tester instructions in the instruction storage unit or an instruction of the user program. A transfer control unit transmits the tester instruction in the instruction storage unit to the tester in accordance with the set transfer mode.

Abstract: A testing device has plural pin electronics substrates and a control substrate. The control substrate includes a first instruction code memory storing an instruction code, a first program counter incrementing a count in synchronization with a clock, a code analysis circuit analyzing the instruction code read from the first instruction code memory in accordance with a counter value, and a control data output control circuit outputting control data for controlling the pin electronics substrates in accordance with the instruction code. Each pin electronics substrate includes a first pin memory storing pin data, a second program counter incrementing a count in synchronization with the clock, and a pin data output control circuit adjusting, based on control data, the count value of the second program counter and outputting pin data read from the first pin memory, the pin data being dependent on the count value of the second program counter.

Abstract: A program counter circuit is composed of two kinds of registers, a down counter, an up counter, a selector, and a logic circuit. The two kinds of registers hold a pre-jump PC value and a post-jump PC value of a jump that is prescribed by a program. The down counter holds the number of repetitions of a repeat sequence that is prescribed by the program. The up counter holds a PC value that is counted up for each clock pulse. The selector selects, as a PC value to be output next, the post-jump PC value or the value that is held by the up counter. The logic circuit refers to the output value of the program counter and the output values of the registers and the down counter, and generates a signal that instructs the selector what PC value should be selected as the next output value.

Abstract: A test pattern generation circuit for use with a self-diagnostic circuit which produces a test pattern through use of a microinstruction code, which includes a memory device RAM/ROM which temporarily stores the microinstruction code and outputs two different instruction codes within one clock cycle; a selector SEL which receives output from the memory device and selectively delays the two instruction codes, thereby outputting one code; and a pattern generation circuit PG which produces a test pattern corresponding to output from the selector.

Abstract: A program counter circuit is composed of two kinds of registers, a down counter, an up counter, a selector, and a logic circuit. The two kinds of registers hold a pre-jump PC value and a post-jump PC value of a jump that is prescribed by a program. The down counter holds the number of repetitions of a repeat sequence that is prescribed by the program. The up counter holds a PC value that is counted up for each clock pulse. The selector selects, as a PC value to be output next, the post-jump PC value or the value that is held by the up counter. The logic circuit refers to the output value of the program counter and the output values of the registers and the down counter, and generates a signal that instructs the selector what PC value should be selected as the next output value.

Abstract: In the testing device of a semiconductor integrated circuit, each of the logics is provided with the JTAG circuit includes: a boundary scan register that executes a test of the logic in accordance with a test data input and stores a test result, a data register, a pseudo bypass register having a bypassing function of the test data input, a first selector connected to the data register and the pseudo bypass register, which selectively takes out outputs of the registers, a bypass register having the bypassing function of the test data input, an instruction register for giving an operation command, and a second selector connected to the boundary scan register, the first selector, the bypass register, and the instruction register, which is selectively controlled by the instruction register. In this construction, the output from the second selector of a specific logic is connected to the input of another logic.

Abstract: A test pattern generation circuit for use with a self-diagnostic circuit which produces a test pattern through use of a microinstruction code, which includes a memory device RAM/ROM which temporarily stores the microinstruction code and outputs two different instruction codes within one clock cycle; a selector SEL which receives output from the memory device and selectively delays the two instruction codes, thereby outputting one code; and a pattern generation circuit PG which produces a test pattern corresponding to output from the selector.

Abstract: When a level of an asynchronous internal clock enabling signal asynchronous with an external clock signal is risen just after or just before a level change of the external clock signal, a for-synchronization-circuit enabling signal synchronized with the external clock signal is produced in a control signal producing circuit on condition that a level of the for-synchronization-circuit enabling signal is risen at a time which is later than the level change of the external clock signal by two clocks of the external clock signal. Therefore, a reset time-period from the level change of the external clock signal to the level change of the for-synchronization-circuit enabling signal, is obtained. A synchronization circuit is reset in the reset time-period according to the external clock signal and the asynchronous internal clock enabling signal, and, a test signal is produced in the synchronization circuit from the for-synchronization-circuit enabling signal after the reset time-period passes.