Patents by Inventor Yukikazu Tanaka

Yukikazu Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387242
    Abstract: A gate insulating layer includes a first gate insulating film including an organic polymer compound and covering a second part of a support surface and a gate electrode layer, and second gate insulating film including an inorganic silicon compound and sandwiched between the first gate insulating film and a semiconductor layer. The second gate insulating film has a thickness of 2 nm or greater and 30 nm or less, and the second gate insulating film has a hydrogen content of 5 at % or more and 13 at % or less so as to enhance the electrical durability of the thin film transistor against bending of the flexible substrate.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Applicant: TOPPAN Inc.
    Inventors: Chihiro IMAMURA, Manabu ITO, Yukikazu TANAKA
  • Patent number: 8410482
    Abstract: Disclosed in a semiconductor device including a substrate, a first transistor, a second transistor, and a first source electrode and a first drain electrode of the first transistor are arranged along a first direction and a second source electrode and a second drain electrode of the second transistor are arranged in a reverse order of the first source electrode and the first drain electrode along the first direction, the first source electrode and the second source electrode are connected by a source connecting wiring, the first drain electrode and the second drain electrode are connected by a drain connecting wiring, a first gate electrode and a second gate electrode are connected by a gate connecting wiring and the source connecting wiring and the drain connecting wiring are provided at positions except a region overlapped with the first gate electrode, the second gate electrode and the gate connecting wiring.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: April 2, 2013
    Assignee: Casio Computer Co., Ltd.
    Inventors: Kunihiro Matsuda, Hiroshi Matsumoto, Yukikazu Tanaka
  • Publication number: 20110241002
    Abstract: Disclosed in a semiconductor device including a substrate, a first transistor, a second transistor, and a first source electrode and a first drain electrode of the first transistor are arranged along a first direction and a second source electrode and a second drain electrode of the second transistor are arranged in a reverse order of the first source electrode and the first drain electrode along the first direction, the first source electrode and the second source electrode are connected by a source connecting wiring, the first drain electrode and the second drain electrode are connected by a drain connecting wiring, a first gate electrode and a second gate electrode are connected by a gate connecting wiring and the source connecting wiring and the drain connecting wiring are provided at positions except a region overlapped with the first gate electrode, the second gate electrode and the gate connecting wiring.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 6, 2011
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Kunihiro MATSUDA, Hiroshi Matsumoto, Yukikazu Tanaka
  • Publication number: 20110227081
    Abstract: A pixel circuit substrate includes: a pixel electrode; a first drive element connected to one side of the pixel electrode; a second drive element that is connected to the first drive element in parallel and also is connected to the other side opposite to the one side of the pixel electrode.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 22, 2011
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Kunihiro MATSUDA, Hiroshi Matsumoto, Yukikazu Tanaka
  • Patent number: 7580014
    Abstract: A display apparatus includes a substrate, a plurality of pixel electrodes which are arrayed on a side of one surface of the substrate, EL layers each of which is formed on a corresponding one of the pixel electrodes, and an counter electrode which is formed on the EL layers. An auxiliary electrode is electrically connected to the counter electrode and overlaps portions between the pixel electrodes.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 25, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Yukikazu Tanaka, Tomoyuki Shirasaki
  • Publication number: 20040263441
    Abstract: A display apparatus includes a substrate, a plurality of pixel electrodes which are arrayed on a side of one surface of the substrate, EL layers each of which is formed on a corresponding one of the pixel electrodes, and an counter electrode which is formed on the EL layers. An auxiliary electrode is electrically connected to the counter electrode and overlaps portions between the pixel electrodes.
    Type: Application
    Filed: June 14, 2004
    Publication date: December 30, 2004
    Applicant: Casio Computer Co., Ltd.
    Inventors: Yukikazu Tanaka, Tomoyuki Shirasaki
  • Patent number: 5585950
    Abstract: A pair of polarizing plates are disposed on two sides of an STN type liquid crystal cell constituted by a liquid crystal twist-aligned at a twist angle of 180.degree. to 270.degree.. A retardation plate is disposed between one of the polarizing plates and the liquid crystal cell in such a manner that the optical axis of the retardation plate crosses the transmission axis of the adjacent polarizing plate at 35.degree. to 55.degree.. The pair of polarizing plates are arranged such that their transmission axes are parallel to each other. The liquid crystal cell is arranged such that the optical axis of the retardation plate crosses the aligning direction of the liquid crystal molecules on the substrate side adjacent to the retardation plate at a predetermined angle. A driving circuit is connected to the liquid crystal cell.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: December 17, 1996
    Assignee: Casio Computer Co., Ltd.
    Inventors: Toshiharu Nishino, Toshihiko Mori, Yasushi Nishida, Kazuyoshi Arai, Yukikazu Tanaka, Hideshi Sato