Abstract: The invention relates to electronic device having an operation temperature range, wherein the electronic device comprises a tunable capacitor (CST) comprising a first electrode (BE), a second electrode (TE), and a dielectric (FEL) arranged between the first electrode (BE) and the second electrode (TE). The dielectric (FEL) comprises dielectric material (FEL) having a value of a relative dielectric constant (?r) varying at least within the operation temperature range. The electronic device further comprises a temperature varying means (RES) being thermally coupled to the tunable capacitor for providing a temperature of the dielectric (FEL) causing a predetermined capacitance of the tunable capacitor (CST). The invention, which relies on the idea of varying temperature to vary a capacitance of a capacitor stack, provides an alternative tunable capacitor type for the known types.

Abstract: A capacitor (110), wherein the capacitor (110) comprises a capacitor dielectric (112) comprising a dielectric matrix (114) of a first value of permittivity, and a plurality of nanoclusters (116) of a second value of permittivity which is larger than the first value of permittivity which are at least partially embedded in the dielectric matrix (114), wherein the plurality of nanoclusters (116) are formed in the dielectric matrix (114) by spontaneous nucleation.

Abstract: A semiconductor device includes a channel region 18 of semiconductor, a conductive gate electrode 12 adjacent to the channel region 18 and a gate dielectric 10 between the conductive gate electrode 12 and the channel region 18. The gate dielectric 10 is formed of a material that is a ferroelectric in bulk but in a superparaelectric state. The gate dielectric may be for instance of formula AXO3, where A is a group I or II element, and X is titanium, niobium, zirconium and/or hafnium. Such a gate dielectric 10 may be formed for example by low temperature deposition of the gate dielectric 10 or by using dopants of metal oxides to prevent domain growth, or both.

Abstract: A capacitor (110), wherein the capacitor (110) comprises a capacitor dielectric (112) comprising a dielectric matrix (114) of a first value of permittivity, and a plurality of nanoclusters (116) of a second value of permittivity which is larger than the first value of permittivity which are at least partially embedded in the dielectric matrix (114), wherein the plurality of nanoclusters (116) are formed in the dielectric matrix (114) by spontaneous nucleation.

Abstract: The invention relates to a semiconductor device includes a substrate (1000; 2000), a solar cell (1910; 2910) formed on the substrate (1000; 2000) and a battery (1900; 2900) formed on the substrate, the battery comprising a plurality of trench batteries in a plurality of corresponding trenches (1400; 2400) in the substrate (1000; 2000). The solar cell can include a silicon solar cell (1910) comprising a plurality of p-n junctions for, during use, receiving incident light and converting at least part of the received incident light into an electrical current. Alternatively, the solar cell can include an electrochemical cell (2910) for, during use, receiving incident light and converting at least part of the received incident light into an electrical current. The invention further relates to a manufacturing method for a semiconductor device. The invention further relates to an apparatus comprising a semiconductor device.

Abstract: The invention relates to electronic device having an operation temperature range, wherein the electronic device comprises a tunable capacitor (CST) comprising a first electrode (BE), a second electrode (TE), and a dielectric (FEL) arranged between the first electrode (BE) and the second electrode (TE). The dielectric (FEL) comprises dielectric material (FEL) having a value of a relative dielectric constant (?r) varying at least within the operation temperature range. The electronic device further comprises a temperature varying means (RES) being thermally coupled to the tunable capacitor for providing a temperature of the dielectric (FEL) causing a predetermined capacitance of the tunable capacitor (CST). The invention, which relies on the idea of varying temperature to vary a capacitance of a capacitor stack, provides an alternative tunable capacitor type for the known types.

Abstract: The present invention relates to a MEMS, being developed for e.g. a mobile communication application, such as switch, tunable capacitor, tunable filter, phase shifter, multiplexer, voltage controlled oscillator, and tunable matching network. The volume change of phase-change layer is used for a bi-stable actuation of the MEMS device. The MEMS device comprises at least a bendable cantilever, a phase change layer, and electrodes. A process to implement this device and a method for using is given.

Abstract: The present invention relates to particles comprising a core and a shell, and a method of producing said particle. The core comprises mainly TiN, wherein the shell comprises mainly TiO2. The shell has a thickness of more than 5 nm and of less than 200 nm. The core size is preferably larger than 10 nm and is preferably smaller than 100 um.

Abstract: The present invention relates to particles comprising a core and a shell, a method of producing said particle, various uses of said particle as well as various products comprising said particle. The particle according to the invention may be used as photocatalyst, as antibacterial agent, as cleaning agent, as anti-fogging agent and as decomposing agent. Furthermore the particle is applicable as solar cells.

Abstract: A semiconductor device includes a channel region 18 of semiconductor, a conductive gate electrode 12 adjacent to the channel region 18 and a gate dielectric 10 between the conductive gate electrode 12 and the channel region 18. The gate dielectric 10 is formed of a material that is a ferroelectric in bulk but in a superparaelectric state. The gate dielectric may be for instance of formula AXO3, where A is a group I or II element, and X is titanium, niobium, zirconium and/or hafnium. Such a gate dielectric 10 may be formed for example by low temperature deposition of the gate dielectric 10 or by using dopants of metal oxides to prevent domain growth, or both.

Abstract: A metal-oxide-semiconductor (MOS) device having a body of single-crystal strontium titanate or barium titanate (10) is provided in which the body comprises a doped semiconductor region (24) adjacent a dielectric region (26). The body may further comprise a doped conductive region separated from the semiconductor region by the dielectric region. The material characteristics of single-crystal strontium titanate when doped in various ways are exploited to provide the insulating, conducting and semiconducting components of a MOS stack. Advantageously, the use of a single body avoids the presence of interface layers between the stack components which improves the characteristics of MOS devices such as field effect transistors.

Abstract: A method of manufacturing an electronic device is provided wherein an interconnect is made using 193 nm lithography. No deformation of the desired linewidth takes place in that during a plasma gas is used which dissociates in low-weight ions. The electronic device is particularly an integrated circuit.

Abstract: A biosensor device (10) for detecting of molecules of an analyte in a sample (23) comprising: an identification element (18) comprising at least one self assembling monolayer (26) having a first surface, a transducer element (20) comprising a metal electrode (34) for receiving an electric signal from the reaction of the molecules in the sample with the at least one self assembling monolayer (26), and at least one electronic element (14, 16) for receiving the electric signal from the transducer element (20), for processing, and/or storing the electric signal. The at least one self-assembling monolayer (26) comprises at least one carboxylic acid-group for coupling the at least one self-assembling monolayer (26) to the surface (32) of the metal electrode (34).

Abstract: This invention relates to a method of manufacturing a semiconductor device. In this method, a semiconductor device is provided comprising a substrate (10), the substrate (10) being covered with a low-k precursor layer (20) having a surface (25). After this step, a partial curing step is performed in which a dense layer (30) is formed at or near the surface (25) of a low-k precursor layer (20). This dense layer (30) can act as a protective layer (30). The low-k precursor material (20) is chosen from a group of materials having the property that they are applicable in a non-cured or partially cured state. The main advantage of this method is that no separate protective layer (30) needs to be provided to the low-k precursor layer (20), because the dense layer (30) is formed out of the low-k precursor layer (20) itself. The dense layer (30) therefore has a good adhesion to the low-k precursor layer (20).

Abstract: A metal-oxide-semiconductor (MOS) device having a body of single-crystal strontium titanate or barium titanate (10) is provided in which the body comprises a doped semiconductor region (24) adjacent a dielectric region (26). The body may further comprise a doped conductive region separated from the semiconductor region by the dielectric region. The material characteristics of single-crystal strontium titanate when doped in various ways are exploited to provide the insulating, conducting and semiconducting components of a MOS stack. Advantageously, the use of a single body avoids the presence of interface layers between the stack components which improves the characteristics of MOS devices such as field effect transistors.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) and a substrate (2) comprising at least one semiconductor element (3) and provided with at least one connection region (4) and an overlying stripe-shaped connection conductor (5) which is connected to the connection region (4), which connection conductor and connection region are both recessed in a dielectric material, where subsequently a first dielectric layer (6), a hard mask layer (7), and a second dielectric layer (8) are deposited on the semiconductor body (1), where at the location of the connection region (4) to be formed, a via (44) is formed in the first dielectric layer (6) by means of plasma etching using a plasma containing a compound of carbon and fluor, and in the presence of a patterned photoresist layer deposited on top of the structure and at the location of the connection conductor (6) to be formed, a trench (55) is formed in the second dielectric layer (8) by means of plasma etching

Abstract: A method of manufacturing an electronic device is provided wherein an interconnect is made using 193 nm lithography. No deformation of the desired linewidth takes place in that during a plasma gas is used which dissociates in low-weight ions. The electronic device is particularly an integrated circuit.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) and a substrate (2) comprising at least one semiconductor element (3) and provided with at least one connection region (4) and an overlying stripe-shaped connection conductor (5) which is connected to the connection region (4), which connection conductor and connection region are both recessed in a dielectric material, where subsequently a first dielectric layer (6), a hard mask layer (7), and a second dielectric layer (8) are deposited on the semiconductor body (1), where at the location of the connection region (4) to be formed, a via (44) is formed in the first dielectric layer (6) by means of plasma etching using a plasma containing a compound of carbon and fluor, and in the presence of a patterned fotoresist layer deposited on top of the structure and at the location of the connection conductor (6) to be formed, a trench (55) is formed in the second dielectric layer (8) by means of plasma etching,

Abstract: An information offering method including: disclosing summary information about a designated product via a designated communication line; judging whether or not the user reading said summary information disclosed by said summary information disclosing step and desiring to read detailed product information about the product about which said summary information is disclosed is a user who is permitted to read detailed information; and disclosing detailed information about the product about which said summary information is disclosed, to the user who is judged to be permitted to read detailed information by said judgment step.

Abstract: An object of the present invention is to provide a dielectric ceramic composition in which a volume changing ratio of the electrostatic capacity is within ±0.3% over a wide temperature range of −55 to +125° C., it satisfies the NPO characteristics regulated by EIA standard, the dielectric constant is high as 75 or more and the Q value of 2000 or higher and it is capable of subjecting to sintering at a low temperature of 1100 to 1150° C. The dielectric ceramic composition of the present invention is a (Ba Ca Sr Nd Gd)TiO3 series composition and to the composition was added and contained 1.0 to 5.0% by weight of ZnSiTiO5, 1.0 to 5.0% by weight of ZnSi2TiO7 or 1.0 to 5.0% by weight of CaSiTiO5 based on the weight of the composition.