Patents by Inventor Yukiko Haraguchi

Yukiko Haraguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor wafer, method of manufacturing the same and semiconductor device
    Patent number: 7964475
    Abstract: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Yukiko Haraguchi, Takahiro Kumakawa, Takashi Yui, Kazumi Watase
  • SEMICONDUCTOR WAFER, METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE
    Publication number: 20080135975
    Abstract: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.
    Type: Application
    Filed: December 6, 2007
    Publication date: June 12, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukiko Haraguchi, Takahiro Kumakawa, Takashi Yui, Kazumi Watase