Patents by Inventor Yukiko Manabe

Yukiko Manabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device comprising a memory cell group having a gate width larger than a second memory cell group
    Patent number: 8576634
    Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: November 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Fumitoshi Ito, Yoshiyuki Kawashima, Takeshi Sakai, Yasushi Ishii, Yasuhiro Kanamaru, Takashi Hashimoto, Makoto Mizuno, Kousuke Okuyama, Yukiko Manabe
  • SEMICONDUCTOR DEVICE
    Publication number: 20100202205
    Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.
    Type: Application
    Filed: April 20, 2010
    Publication date: August 12, 2010
    Inventors: Fumitoshi Ito, Yoshiyuki Kawashima, Takeshi Sakai, Yasushi Ishii, Yasuhiro Kanamaru, Takashi Hashimoto, Makoto Mizuno, Kousuke Okuyama, Yukiko Manabe
  • Semiconductor device
    Patent number: 7719052
    Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: May 18, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Fumitoshi Ito, Yoshiyuki Kawashima, Takeshi Sakai, Yasushi Ishii, Yasuhiro Kanamaru, Takashi Hashimoto, Makoto Mizuno, Kousuke Okuyama, Yukiko Manabe
  • SEMICONDUCTOR DEVICE
    Publication number: 20080151629
    Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.
    Type: Application
    Filed: January 25, 2008
    Publication date: June 26, 2008
    Inventors: Fumitoshi ITO, Yoshiyuki Kawashima, Takeshi Sakai, Yasushi Ishii, Yasuhiro Kanamaru, Takashi Hashimoto, Makoto Mizuno, Kousuke Okuyama, Yukiko Manabe
  • Semiconductor device
    Patent number: 7349250
    Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: March 25, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Fumitoshi Ito, Yoshiyuki Kawashima, Takeshi Sakai, Yasushi Ishii, Yasuhiro Kanamaru, Takashi Hashimoto, Makoto Mizuno, Kousuke Okuyama, Yukiko Manabe
  • Semiconductor device
    Publication number: 20060077713
    Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.
    Type: Application
    Filed: July 15, 2005
    Publication date: April 13, 2006
    Inventors: Fumitoshi Ito, Yoshiyuki Kawashima, Takeshi Sakai, Yasushi Ishii, Yasuhiro Kanamaru, Takashi Hashimoto, Makoto Mizuno, Kousuke Okuyama, Yukiko Manabe
  • Nonvolatile semiconductor memory
    Publication number: 20020153555
    Abstract: The write performance and erasion performance of a nonvolatile semiconductor memory having as its memory elements MOSFETs in each of which a floating gate electrode is formed on each of the two sidewalls of a control gate electrode are to be improved, and the read performance is also to be improved. Part of the control gate electrode is extended above the floating gate electrodes on its two sidewalls. A source region and a drain region are formed alongside the outer boundaries of the floating gate electrodes so,that electric charges can be separately injected into the two floating gate electrodes.
    Type: Application
    Filed: April 24, 2002
    Publication date: October 24, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Yukiko Manabe, Kousuke Okuyama, Tomohiko Oouchi, Takashi Takeuchi
  • Nonvolatile semiconductor memory
    Publication number: 20020040992
    Abstract: The write performance and erasion performance of a nonvolatile semiconductor memory having as its memory elements MOSFETs in each of which a floating gate electrode is formed on each of the two sidewalls of a control gate electrode are to be improved, and the read performance is also to be improved. Part of the control gate electrode is extended above the floating gate electrodes on its two sidewalls. A source region and a drain region are formed alongside the outer boundaries of the floating gate electrodes so that electric charges can be separately injected into the two floating gate electrodes.
    Type: Application
    Filed: July 17, 2001
    Publication date: April 11, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Yukiko Manabe, Kousuke Okuyama, Tomohiko Oouchi, Takashi Takeuchi