Abstract: A program counter (12) updates an address by adding a first value or a second value. A code select circuit (14) selects, in accordance with the address of the program counter (12), one of an insert code retained in an insert code register set block (17) and corresponding to the address specified by the program counter (12), and an original code stored in a flash control code ROM (13) and having the address specified by the program counter (12). An instruction execution unit (15) executes the selected code. At least one of a plurality of original codes and the insert code is a multicycle instruction. The program counter (14) stops update of the address when the multicycle instruction is executed.

Abstract: An input buffer circuit includes a first input buffer and a second input buffer. The first input buffer receives an external data signal and a reference potential to output an internal data signal. The second input buffer receives external data signals complementary to each other to output the internal data signal. The input buffer circuit causes either the first or second input buffer to operate in response to a control signal outputted from a control circuit. Due to this, this semiconductor memory device can correspond to various types of data processing systems.

Abstract: In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to GIO<7> and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

Abstract: This DDR SDRAM, in the normal operation mode, performs a writing operation having a writing latency and, in the testing mode, performs a writing operation without having a writing latency by receiving a data strobe signal and a data signal one clock cycle before a writing command. Therefore, the testing time is short even if the test is carried out at a low frequency.

Abstract: A memory cell is formed of a sense access transistor for data sensing, a restore access transistor for data restoration and a memory capacitor for data storage. Sense access transistor couples the memory capacitor to a sense bit line according to a signal on a sense word line. The restore access transistor couples the memory capacitor to a restore bit line provided separate from the sense bit line according to a signal on a restore word line. Electric charges in the memory capacitor are transferred to a sense amplifier through the sense bit line and sense data in a sense amplifier is transferred to original memory capacitor through a restore amplifier and the restore access transistor. Output signal lines of the sense amplifier are electrically isolated from the sense and restore bit lines. Thereby, it is possible to reduce the access time of a semiconductor memory device.

Abstract: An input buffer circuit includes a first input buffer and a second input buffer. The first input buffer receives an external data signal and a reference potential to output an internal data signal. The second input buffer receives external data signals complementary to each other to output the internal data signal. The input buffer circuit causes either the first or second input buffer to operate in response to a control signal outputted from a control circuit. Due to this, this semiconductor memory device can correspond to various types of data processing systems.

Abstract: In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to GIO<7> and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

Abstract: In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between global I/O lines GIO<0> to GIO<7> and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

Abstract: This DDR SDRAM, in the normal operation mode, performs a writing operation having a writing latency and, in the testing mode, performs a writing operation without having a writing latency by receiving a data strobe signal and a data signal one clock cycle before a writing command. Therefore, the testing time is short even if the test is carried out at a low frequency.

Abstract: A DLL circuit generates a control clock specifying an operating timing of a data output buffer according to an external clock. The DLL circuit includes a replica delay time adjusting section and a phase control section. The phase control section controls such that a feedback clock and the external clock becomes in phase. The replica delay time adjusting section adjusts a delay time of the feedback clock behind the control clock according to an operating condition serving as a factor for changing a processing time of the data output buffer.

Abstract: A DLL circuit generates a control clock specifying an operating timing of a data output buffer according to an external clock. The DLL circuit includes a replica delay time adjusting section and a phase control section. The phase control section controls such that a feedback clock and the external clock becomes in phase. The replica delay time adjusting section adjusts a delay time of the feedback clock behind the control clock according to an operating condition serving as a factor for changing a processing time of the data output buffer.

Abstract: A semiconductor integrated circuit includes a DLL circuit generating an internal clock signal, a plurality of clock generators generating respective output clock signals based on the internal clock signal, a plurality of output buffers outputting to a plurality of data input/output pins data according to corresponding output clock signals respectively, and a selection circuit. The selection circuit outputs a code signal for allowing the timing of the earliest output clock signal to conform to the timing of the latest output clock signal. A predetermined clock generator adjusts the timing of the output clock signal according to the code signal.

Abstract: A semiconductor integrated circuit includes a DLL circuit generating an internal clock signal, a plurality of clock generators generating respective output clock signals based on the internal clock signal, a plurality of output buffers outputting to a plurality of data input/output pins data according to corresponding output clock signals respectively, and a selection circuit. The selection circuit outputs a code signal for allowing the timing of the earliest output clock signal to conform to the timing of the latest output clock signal. A predetermined clock generator adjusts the timing of the output clock signal according to the code signal.

Abstract: It is possible to recover gallium and indium efficiently and at a low cost from solutions containing traces of gallium and indium. In particular, jarosite is produced by performing a specific treatment on a solution obtained by a two-stage neutralization treatment during the zinc leached residue treatment step of wet zinc refining, or on another solution containing traces of gallium and indium; the gallium and indium are separated and concentrated; an alkali is added to the jarosite; and the gallium is separated and concentrated by leaching. Calcium hydroxide or magnesium hydroxide is optionally added to the jarosite leached solution to perform purifying, sulfuric acid is added to the purified solution, neutralization is performed, basic gallium sulfate is precipitated, the precipitate is subjected to alkali leaching, and the gallium in the leached solution is electrolytically extracted, yielding metallic gallium.

Abstract: A semiconductor memory device includes an output control signal generation circuit for generating an output control signal to designate initiation of data output according to an external control signal, and a boosting circuit boosting an external power supply voltage. Each of the plurality of output control circuits generates an output permit signal with the output level of the boosting circuit as the activation level in response to activation of an output control signal. The output permit signals are transmitted to a plurality of output circuits by a corresponding one of a plurality of signal lines. Each of the plurality of output circuits drives the potential of a corresponding output terminal according to a read out data signal and an output permit signal.