Abstract: A semiconductor device comprises a memory cell transistor and a select transistor. An N-type first diffusion layer area is formed below side walls formed on the sides of the memory cell transistor. An N-type second diffusion layer area is formed in an area different from the diffusion layer area. A gate of the select transistor is provided above a channel area between the first diffusion layer area and the second diffusion layer area.

Abstract: A semiconductor device in which a nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate includes a first conductive layer, a first interlevel insulating film, a second conductive layer, and a control gate electrode of the nonvolatile memory cell. The first conductive layer is formed on the semiconductor substrate via a tunnel insulating film, and patterned into a predetermined shape. The first interlevel insulating film is formed on the semiconductor substrate so as to cover the field effect transistor, and has a first opening for exposing the surface of the first conductive layer. The second conductive layer is formed on the first conductive layer inside the first opening, and patterned into a predetermined shape. The control gate electrode of the nonvolatile memory cell is formed on the second conductive layer via an internal insulating film patterned into a predetermined shape.

Abstract: A tunnel barrier structure includes a first semiconductor ridged portion having a grooved first top surface; an insulating layer burying the groove, the insulating layer having a first upper surface which is higher in level than the first top surface of the first semiconductor ridged portion, the insulating layer having side walls extending upwardly from edges of the first top surface of the first semiconductor ridged portion; side wall insulating films provided on the side walls; and a tunnel insulating film provided on the first top surface of the first semiconductor ridged portion, the tunnel insulating film being defined by the side wall insulating films.

Abstract: To provide a semiconductor memory device in which no separation of a silicide layer formed on a control gate takes place and a process for manufacturing the same. A gate dielectric layer and floating gate (4 in FIG. 4) are formed on a silicon substrate. A sidewall made of polysilicon (7 in FIG. 4) is disposed on the lateral side of the floating gate in such a manner that a stop oxide layer (6a in FIG. 4) which functions as an etching stop for the polysilicon is sandwiched between the floating gate and the sidewall. A control gate (8 in FIG. 4) is laminated on the upper side of the floating gate having a step which is sloped by the sidewall in such a manner that an ONO layer (5 in FIG. 4) is sandwiched between the floating gate and the control gate.

Abstract: A semiconductor device in which a nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate includes a first conductive layer, a first interlevel insulating film, a second conductive layer, and a control gate electrode of the nonvolatile memory cell. The first conductive layer is formed on the semiconductor substrate via a tunnel insulating film, and patterned into a predetermined shape. The first interlevel insulating film is formed on the semiconductor substrate so as to cover the field effect transistor, and has a first opening for exposing the surface of the first conductive layer. The second conductive layer is formed on the first conductive layer inside the first opening, and patterned into a predetermined shape. The control gate electrode of the nonvolatile memory cell is formed on the second conductive layer via an internal insulating film patterned into a predetermined shape.

Abstract: To provide a semiconductor memory device in which no separation of a silicide layer formed on a control gate takes place and a process for manufacturing the same. A gate dielectric layer and floating gate (4 in FIG. 4) are formed on a silicon substrate. A sidewall made of polysilicon (7 in FIG. 4) is disposed on the lateral side of the floating gate in such a manner that a stop oxide layer (6a in FIG. 4) which functions as an etching stop for the polysilicon is sandwiched between the floating gate and the sidewall. A control gate (8 in FIG. 4) is laminated on the upper side of the floating gate having a step which is sloped by the sidewall in such a manner that an ONO layer (5 in FIG. 4) is sandwiched between the floating gate and the control gate.

Abstract: A semiconductor device in which a nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate includes a first conductive layer, a first interlevel insulating film, a second conductive layer, and a control gate electrode of the nonvolatile memory cell. The first conductive layer is formed on the semiconductor substrate via a tunnel insulating film, and patterned into a predetermined shape. The first interlevel insulating film is formed on the semiconductor substrate so as to cover the field effect transistor, and has a first opening for exposing the surface of the first conductive layer. The second conductive layer is formed on the first conductive layer inside the first opening, and patterned into a predetermined shape. The control gate electrode of the nonvolatile memory cell is formed on the second conductive layer via an internal insulating film patterned into a predetermined shape.

Abstract: The present invention provides a tunnel barrier structure comprising: a first semiconductor ridged portion having a first top surface, and said first semiconductor ridged portion being defined by a groove; an insulating layer burying the groove, and the insulating layer having a first upper surface which is higher in level than the first top surface of the first semiconductor ridged portion, and the insulating layer having side walls extending upwardly from edges of the first top surface of the first semiconductor ridged portion; side wall insulating films provided on the side walls; and a tunnel insulating film provided on the first top surface of the first semiconductor ridged portion, and the tunnel insulating film being defined by the side wall insulating films.

Abstract: A high-voltage lateral field effect transistor has a lightly doped n-type extended drain region depleted by depletion layers extending from a p-n junction between the lightly doped n-type extended drain region and a p-type silicon substrate and a p-n junction between the lightly doped extended drain region and a p-type impurity region formed in a surface portion thereof, and an n-type step-down region contiguous with the lightly doped n-type extended drain region is formed in a surface of the p-type impurity region so as to permit a step-down drain voltage lower than the drain voltage to be transmitted therefrom, thereby preventing damage to a gate insulating layer of a field effect transistor.

Abstract: The present invention provides a MOSFET semiconductor device having a higher breakdown voltage. The MOSFET semiconductor device includes a p-type substrate having an n-type drain region, an n.sup.- -type drain region located adjacent to the n-type drain region, an n.sup.+ -type drain layer located within the n-type drain region and at a surface of the p-type substrate, a p-type top layer located adjacent to the n.sup.- -type drain region and at a surface of the p-type substrate, an n.sup.+ -type source region and a p.sup.+ -type back gate, and a layout pattern constituted of the above mentioned regions and layers includes straight portions and curved portions. The MOSFET semiconductor device is characterized by that the n-type drain region is formed so that the n-type drain region overlaps the p-type top layer in the straight portions of the layout pattern and does not overlap the p-type top layer in the curved portions of the layout pattern.

Abstract: This invention relates to an improvement of a high power mos device which includes a plurality of power MOSFETs whose drain regions and source regions are respectively connected in common with each other and respectively receive on-off control voltages to the respective gate regions, and circuits for generating the control voltages. When short-circuiting occurs between the gate and the source in either of these power MOSFETs, a gate current detection and interruption circuit is inserted between a control voltage source and the gate so as to interrupt the supply of the control voltage to the gate. With such an arrangement it becomes possible to dissolve adverse effect due to the short-circuiting between the gate and the source, which was not possible in the prior device of this kind, and to improve the reliability of the monolithic power MOSIC device.