Abstract: Disclosed is a memory having a p-type semiconductor substrate having a high impurity concentration a p-type semiconductor layer is formed on thereof; a groove which is formed so as to extend from a surface of the semiconductor layer to a position inside the semiconductor substrate; an impurity diffused region which is formed on portions of the semiconductor layer and the semiconductor substrate which define the groove; and an electrode which is formed from the groove to level at least above an opening of the groove through capacitor insulation film, the impurity diffused region, capacitor insulation film and electrode constituting trenched capacitor in which the electrode serves first capacitor electrode and the impurity diffused region serves as a second capacitor electrode.

Abstract: Each end of a power wiring is connected to a first or a second power supply circuit, respectively. These two power supply circuits are activated alternately allowing for some time-overlap. As a result, current flowing in the wiring changes its flowing direction alternately to prevent the degradation of the wiring due to the electro-migration phenomena.

Abstract: A memory device having an operating function includes a memory cell array, a register, and a logical opeation circuit. The memory cell array has memory cells arranged in a matrix form of m rows .times.n columns. Data readout or write-in operation with respect to the memory cell array is effected in the unit of n bits of one row. The register has a bit width corresponding to one row of the memory cell array. Data of one row is read out from the memory cell array and is processed by the logical operation circuit together with data stored in the register. The result of operation is written into a desired row of the memory cell array. The memory cell array, register, and logical operation circuit are formed in the same integrated circuit, thus permitting processing such as picture element processing to be effected inside the integrated circuit, without the need to use an external data bus.

Abstract: The substrate voltages V.sub.1 and V.sub.2 of NMOS and PMOS transistors, respectively, which constitute a CMOS circuit and the source voltages V.sub.3 and V.sub.4 of these transistors have the following relationship:V.sub.1 <V.sub.3 <V.sub.4 <V.sub.2(where V.sub.1 may be equal to V.sub.3 or V.sub.4 may be equal to V.sub.2). In order to maintain the above relationship, it is preferable that internal power supply means are formed on the substrate upon which is also formed the CMOS circuit so that some of the above voltages may be produced.

Abstract: A first wiring layer is formed on a substrate. An insulation layer is formed on the first wiring layer so as to cover with the first wiring layer. A second wiring layer, which acts as a fuse device, is formed on the insulation layer transverse to the first wiring layer. A programming current is directed through the first wiring layer under the second wiring layer which is to be programmed. The heat generated by the programming current is transmitted through the insulation layer to the portion of the second wiring layer which crosses the first wiring layer. As a result, the second wiring layer is melted by the heat and thus disconnected. Alternatively, the heat may form a eutectic mixture with the material of the second wiring layer and a third wiring layer, which is formed on the second wiring layer, to complete the continuity of the second wiring layer.

Abstract: A dynamic read-write random access memory (DRAM) including a memory cell, a word line and a bit line. The memory cell has a capacitor and a MOS transistor which has a gate connected to the word line, a drain terminal connected to the capacitor and a source terminal connected to the bit line. The DRAM further includes a supply circuit for applying to the bit line a voltage level having a value between the voltage level of the word line and the voltage level of the drain terminal of the MOS transistor when the memory cell is not selected, so as to prevent leakage current from flowing through the MOS transistor.

Abstract: Disclosed is a semiconductor memory device which has a transfer transistor of a MOS structure on a surface of a semiconductor body, and a trenched capacitor having a groove which is formed so as to extend from a surface of the semiconductor body to a certain depth thereof and an electrode which is formed from a bottom portion of the groove to at least a level above an opening of the groove, the source region of the transfer transistor being connected to the electrode of the trenched capacitor and the drain region thereof being connected to a bit line.

Abstract: A fuse element is formed on a field insulation film on a semiconductor substrate of n conductivity type in which MOS transistors are formed. A first guard ring region of second conductivity type is provided in the substrate, surrounding the semiconductor substrate region under the fuse element. A second guard ring region of first conductivity type is formed in the substrate, surrounding the first guard ring region. Proper potentials are applied to the first and second guard ring regions.

Abstract: A semiconductor memory device includes: a semiconductor memory which is driven in response to a power source voltage supplied between a power source pad and a ground pad; and a peripheral circuit for executing the readout of data from and the writing of the same in this semiconductor memory. The power source pad is divided into a main power source pad and a back-up power source pad. The peripheral circuit is made operative by a voltage applied between the main power source pad and ground pad. The semiconductor memory is made operative by a main power source voltage which is applied to the main power source pad and is supplied through a first diode, or by a back-up power source voltage which is applied to the back-up power source pad and is supplied through a second diode.

Abstract: A dynamic type semiconductor memory device is disclosed, which comprises an n-type semiconductor layer, at least one memory cell having a capacitor for storing charges of an amount corresponding to a logic value and a first transistor having source and drain regions formed in the surface area of the p-type semiconductor layer and for transferring charges to and from the capacitor, a first drive circuit for applying a voltage to the gate of the first transistor through a word line, a second drive circuit for selectively applying a voltage of one of first and second levels through a bit line and the first transistor to the capacitor, and a bias circuit for applying a voltage to the substrate. The first transistor of the memory device is a p-channel transistor formed in the n-type semiconductor layer which is formed in the surface area of a p-type semiconductor layer. The bias circuit includes a charge pump section for setting the potential of the substrate at a third level lower than the first voltage.

Abstract: The dynamic memory device of the present invention is formed on an integrated semiconductor substrate subjected to alpha radiation and comprises a switching transistor having a switching terminal, an input-output terminal and a memory terminal; a bit line couple to said input-output terminal for supplying a charge to said transistor; a word line coupled to said switching terminal for controlling the switching of said transistor; and, an R-C circuit coupled to the memory terminal and comprising a charge storage capacitor for storing the charge supplied from said bit line and for substantially preventing loss of the stored charge due to particle radiation.

Abstract: A large capacity and high speed semiconductor memory is disclosed. Static memory cell rows are provided so as to correspond to dynamic memory cell rows in a dynamic memory cell array. Information is transferred with transfer means between static memory cells in the static memory cell rows and dynamic memory cells corresponding thereto. Access for a read/write operation externally required is effected to static memory cell rows.

Abstract: A MIS semiconductor integrated circuit is one which contains an internal circuit. In the internal circuit, an externally supplied power source voltage supplied to a power source voltage terminal is supplied to the voltage input terminal of a voltage dropping circuit. The voltage at a voltage output terminal of the voltage dropping circuit is detected by a voltage detecting circuit containing an inverting circuit with a predetermined threshold voltage. The voltage dropping circuit is switch-controlled by applying the detected voltage to the control terminal thereof. The voltage output terminal of the voltage dropping circuit provides an internal power source voltage which is formed by dropping the externally supplied power source voltage. An internal circuit containing MOSFETs with an effective channel length of 1 .mu.m or less is driven by the internal power source voltage.

Abstract: A programmable circuit has a fuse element grounded at one end and melted or not melted according to the data to be programmed and a select circuit for selectively producing either of two signals according to "melted" or "not melted" states of the fuse element. The other end of the fuse element is connected through a switching element to the power source terminal, and through a latch circuit to the select circuit. By turning on the switching element at least one time, a level corresponding to a melted state of the fuse element is latched in the latch circuit.

Abstract: A semiconductor integrated circuit includes a transistor element, an insulating layer formed adjacent to the transistor, and a wiring connected to the transistor element at one end thereof and having a fuse as a part thereof. The wiring is made of monocrystalline silicon and formed on the insulating layer providing a substantially constant burn out current value for the fuse, and thus highly reliable operation of the circuit.

Abstract: A MOS type semiconductor device effectively supplying potential to a substrate region under the channel forming region of the MOS transistor on an insulating substrate. The potential is supplied to the one conductivity type substrate region under the channel forming region which is provided on an insulating substrate and has an extended portion extending in the channel length direction, through a substrate potential take-out region of one conductivity type connecting to the extended substrate. A gate electrode with an extended gate portion is formed on the substrate region through a gate insulating film, so as to cover the substrate region.

Abstract: A MOS type semiconductor device formed on an insulating layer and having a substrate electrode. A first semiconductor layer for forming a MOS type element is formed on the insulating layer and has a substrate region where a channel is to be formed. To this substrate region is connected a second semiconductor layer which is thinner than the first semiconductor layer and which has the same conductivity type as that of the substrate region where the channel is to be formed.

Abstract: A memory circuit comprises a plurality of memory cells and a plurality of sense circuits each including first and second input MOS transistors and first and second load MOS transistors of a first channel type and a load circuit connected to the sense circuit and including first to fourth load MOS transistors of a second channel type. The first and second input MOS transistors have their sources connected to each other and their gates connected to receive a differential input signal therebetween from said memory circuits of the first and second switching transistors which have their sources connected respectively to the drains of said first and second input transistors and their gates connected to a column selection signal. The first and second load MOS transistors have their drains connected in common to the drain of the first switching MOS transistors and their sources connected to each other.

Abstract: A nonvolatile semiconductor memory device having a gate insulating film with a memory function. An impurity layer having the same conductivity type as that of the substrate region is formed in that substrate region, underlying the gate insulating film having a memory function, in which a channel is formed. The impurity layer has an impurity profile in which a peak of an impurity concentration is in the region distanced by 500 .ANG. or less from the surface of the substrate region and the impurity concentration is 1.times.10.sup.18 cm.sup.-3 or less in the region at the depth of 500 .ANG. or more.

Abstract: A nonvolatile semiconductor memory device having floating gate type field effect transistors with floating gate electrodes. In the memory device, a source region, an active region and a drain region are formed in a first semiconductor region. A second semiconductor region is formed so as to electrically be insulated from the first semiconductor region. A floating gate electrode is formed on the first and second semiconductor regions with an insulating film interposed therebetween, respectively. The floating gate electrode faces the second semiconductor region with the insulating film interposed therebetween so that charge may be transferred between the floating gate electrode and second semiconductor region in order to control an amount of charge in the floating gate electrode.