Patents by Inventor Yukimune Watanabe
Yukimune Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11404269Abstract: A single crystal substrate is provided and is characterized in that the single crystal substrate has a foundation substrate provided with a plurality of first grooves, which include a first crystal face and a second crystal face opposed to the first crystal face in an inner face thereof, and the extending direction of which is a<110> direction, and a plurality of second grooves, the extending direction of which intersects with the first grooves, and in which the first grooves are formed in a displaced manner in a depth direction, and a transverse cross-sectional shape of the second groove is a shape in which straight lines are open at an opening angle less than 180°. Further, it is preferred that an angle formed by the first crystal face and the second crystal face is more than 70.6°.Type: GrantFiled: June 28, 2018Date of Patent: August 2, 2022Inventors: Yukimune Watanabe, Noriyasu Kawana
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Patent number: 11142821Abstract: A single crystal substrate is provided and is characterized in that the single crystal substrate has a foundation substrate provided with a plurality of grooves, which include a first crystal face and a second crystal face opposed to the first crystal face in an inner face thereof, and the extending direction of which is a <110> direction, and an angle formed by the first crystal face and the second crystal face is more than 70.6°. Further, it is preferred that the angle formed by the first crystal face and the second crystal face is 100° or more and 176° or less.Type: GrantFiled: June 28, 2018Date of Patent: October 12, 2021Inventors: Yukimune Watanabe, Noriyasu Kawana
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Patent number: 9882010Abstract: A silicon carbide substrate includes a Si substrate (silicon substrate), a SiC base film (silicon carbide base film) which is stacked on the Si substrate and contains silicon carbide, a defective part (through-hole) which passes through the SiC base film, a hole which is located between the Si substrate and the SiC base film corresponding to the defective part, and an oxide film which is provided on the surface of the Si substrate in the hole and contains silicon oxide. Further, on the SiC base film, a SiC grown layer (silicon carbide grown layer) may be formed.Type: GrantFiled: May 12, 2016Date of Patent: January 30, 2018Assignee: SEIKO EPSON CORPORATIONInventor: Yukimune Watanabe
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Patent number: 9758902Abstract: A 3C-SiC epitaxial layer is produced by a production method including: epitaxially growing a first 3C-SiC layer on a Si substrate; oxidizing the first 3C-SiC layer; removing an oxide film on a surface of the 3C-SiC layer; and epitaxially growing a second 3C-SiC layer on the 3C-SiC layer after the oxide film is removed.Type: GrantFiled: October 15, 2014Date of Patent: September 12, 2017Assignee: SEIKO EPSON CORPORATIONInventors: Yukimune Watanabe, Noriyasu Kawana
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Patent number: 9732439Abstract: A method for manufacturing a cubic silicon carbide film includes: a first step of introducing a carbon-containing gas onto a silicon substrate and rapidly heating the silicon substrate to an epitaxial growth temperature of cubic silicon carbide so as to carbonize a surface of the silicon substrate and form a cubic silicon carbide film; and a second step of introducing a carbon-containing gas and a silicon-containing gas onto the cubic silicon carbide film while maintaining the cubic silicon carbide film at the epitaxial growth temperature of cubic silicon carbide, so as to allow further epitaxial growth of the cubic silicon carbide film.Type: GrantFiled: June 11, 2015Date of Patent: August 15, 2017Assignee: SEIKO EPSON CORPORATIONInventor: Yukimune Watanabe
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Patent number: 9536954Abstract: A substrate with a silicon carbide film includes a silicon substrate, a SiC film, and a mask 4. The SiC film has a film 31 including openings 35 on the silicon substrate and a film 32 provided on the upper side of the film 31. The mask 4 has a mask 41 provided on the upper side of the silicon substrate and including openings 45 and a mask 42 covering at least part of the mask 41 located in the openings 35 and the side surfaces of the openings 35 and including openings 46. The width W1 of the opening 45, the thickness T1 (?m) of the mask 41, and the thickness D (?m) of the film 31 at a position corresponding to the opening 45 satisfy the following relationships: T1<tan(54.6°)×W1, and D?tan(54.6°)×W1.Type: GrantFiled: October 29, 2015Date of Patent: January 3, 2017Assignee: SEIKO EPSON CORPORATIONInventor: Yukimune Watanabe
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Patent number: 9362368Abstract: A substrate with a silicon carbide film includes a Si substrate, and a SiC film and a mask stacked on the Si substrate. The SiC film has a first SiC film provided on the upper side of the Si substrate and a second SiC film provided on the upper side of the first SiC film. The mask has a first mask provided on the Si substrate and including an opening (first opening) and a second mask provided on the first SiC film and including an opening (second opening). The width W1 (?m) of the first opening and the thickness T1 (?m) of the first mask satisfy the following relationship: T1<tan(54.6°)×W1.Type: GrantFiled: October 29, 2015Date of Patent: June 7, 2016Assignee: SEIKO EPSON CORPORATIONInventor: Yukimune Watanabe
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Patent number: 9064802Abstract: A method of manufacturing a semiconductor device includes forming a metal oxide on a semiconductor substrate, forming a gate electrode film on the metal oxide, and executing a thermal treatment on the semiconductor substrate provided with the metal oxide and the gate electrode film to crystallize the metal oxide.Type: GrantFiled: May 1, 2008Date of Patent: June 23, 2015Assignee: SEIKO EPSON CORPORATIONInventor: Yukimune Watanabe
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Patent number: 8986464Abstract: A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 105 Pa·S or more and 1014.5 Pa·S or less in a temperature range of 950 to 1400° C.Type: GrantFiled: March 12, 2012Date of Patent: March 24, 2015Assignee: Seiko Epson CorporationInventor: Yukimune Watanabe
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Patent number: 8847236Abstract: A semiconductor substrate includes: a silicon substrate; a monocrystalline silicon carbide film formed on a surface of the silicon substrate; and a stress relieving film formed on the surface of the silicon substrate opposite from the side on which the monocrystalline silicon carbide film is formed, and that relieves stress in the silicon substrate by applying compressional stress to the silicon substrate surface on which the stress relieving film is formed, wherein a plurality of spaces is present in the monocrystalline silicon carbide film in portions on the side of the silicon substrate and along the interface between the monocrystalline silicon carbide film and the silicon substrate.Type: GrantFiled: January 7, 2013Date of Patent: September 30, 2014Assignee: Seiko Epson CorporationInventor: Yukimune Watanabe
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Patent number: 7968396Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.Type: GrantFiled: November 25, 2009Date of Patent: June 28, 2011Assignees: Seiko Epson Corporation, Renesas Technology CorporationInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
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Patent number: 7947560Abstract: A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface between the nickel film and the silicon layer (or the silicon substrate); and after the introduction of the nitrogen, applying heat treatment to the nickel film and the silicon layer (or the silicon substrate) under predetermined conditions to form a nickel disilicide layer.Type: GrantFiled: February 21, 2007Date of Patent: May 24, 2011Assignees: Seiko Epson Corporation, Renesas Technology CorporationInventors: Yukimune Watanabe, Nobuyuki Mise, Shinji Migita
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Patent number: 7713884Abstract: A semiconductor wafer is placed in a chamber of a film-deposition apparatus, and gas in the chamber is exhausted from a gas exhaust outlet. Then, with interrupting the exhaust, an inert gas is introduced into the chamber so that the chamber has a pressure of 133 Pa or higher and lower than 101325 Pa, and then a mixed gas of an inert gas and a source gas for depositing a metal oxide film is introduced into the chamber. Then, after exhausting the gas in the chamber, an oxidation gas is introduced into the chamber to react with the molecules of the source gas absorbed on the semiconductor wafer to form a metal oxide film on the semiconductor wafer. By repeating these steps, a metal oxide film having a desired film thickness is deposited on the semiconductor wafer with a film-thickness distribution by an ALD method.Type: GrantFiled: June 19, 2008Date of Patent: May 11, 2010Assignees: Renesas Technology Corp., Seiko Epson CorporationInventors: Hiromi Ito, Yuuichi Kamimuta, Yukimune Watanabe, Shinji Migita
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Publication number: 20100072551Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.Type: ApplicationFiled: November 25, 2009Publication date: March 25, 2010Applicants: SEIKO EPSON CORPORATION, RENESAS TECHNOLOGY CORPORATIONInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
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Patent number: 7645655Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.Type: GrantFiled: June 5, 2006Date of Patent: January 12, 2010Assignees: Seiko Epson Corporation, Renesas Technology CorporationInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
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Publication number: 20080318439Abstract: A semiconductor wafer is placed in a chamber of a film-deposition apparatus, and gas in the chamber is exhausted from a gas exhaust outlet. Then, with interrupting the exhaust, an inert gas is introduced into the chamber so that the chamber has a pressure of 133 Pa or higher and lower than 101325 Pa, and then a mixed gas of an inert gas and a source gas for depositing a metal oxide film is introduced into the chamber. Then, after exhausting the gas in the chamber, an oxidation gas is introduced into the chamber to react with the molecules of the source gas absorbed on the semiconductor wafer to form a metal oxide film on the semiconductor wafer. By repeating these steps, a metal oxide film having a desired film thickness is deposited on the semiconductor wafer with a film-thickness distribution by an ALD method.Type: ApplicationFiled: June 19, 2008Publication date: December 25, 2008Inventors: Hiromi Ito, Yuuichi Kamimuta, Yukimune Watanabe, Shinji Migita
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Publication number: 20080067590Abstract: It is an object of the present invention to provide a technology which can form a sidewall without deteriorating device characteristics. A gate insulating film formed of a high dielectric constant film and a polysilicon film are formed on a semiconductor substrate. By patterning the polysilicon film, silicon gate electrodes are formed. Subsequently, a laminated film of an aluminum oxide film and a silicon nitride film is formed on the semiconductor substrate. Thereafter, the silicon nitride film is anisotropically dry-etched to leave silicon nitride films only on sidewalls of the silicon gate electrodes. At this time, the aluminum oxide film formed under the silicon nitride film functions as an etching stopper. Then, the exposed aluminum oxide film is wet-etched using diluted hydrofluoric acid.Type: ApplicationFiled: May 11, 2007Publication date: March 20, 2008Inventors: Nobuyuki Mise, Kunihiko Iwamoto, Yukimune Watanabe, Shinji Migita
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Publication number: 20070202692Abstract: A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface between the nickel film and the silicon layer (or the silicon substrate); and after the introduction of the nitrogen, applying heat treatment to the nickel film and the silicon layer (or the silicon substrate) under predetermined conditions to form a nickel disilicide layer.Type: ApplicationFiled: February 21, 2007Publication date: August 30, 2007Applicants: SEIKO EPSON CORPORATION, RENESAS TECHNOLOGY CORPORATIONInventors: Yukimune Watanabe, Nobuyuki Mise, Shinji Migita
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Publication number: 20060284220Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.Type: ApplicationFiled: June 5, 2006Publication date: December 21, 2006Applicants: SEIKO EPSON CORPORATION, THE NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, RENESAS TECHNOLOGY CORPORATIONInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
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Publication number: 20060281273Abstract: A semiconductor device includes a gate electrode disposed on a semiconductor layer via a gate insulating film; a source layer formed in the semiconductor layer to be separated by a first offset length from one end of said gate electrode; a drain layer formed in the semiconductor layer to be separated by a second offset length from the other end of said gate electrode; a first side wall formed at a side wall of said gate electrode at a side of said source layer; and a second side wall formed at the side wall of said gate electrode at a side of said drain layer, wherein the first offset length is shorter than the second offset length, and a length of said first side wall is shorter than a length of said second side wall.Type: ApplicationFiled: June 5, 2006Publication date: December 14, 2006Applicants: SEIKO EPSON CORPORATION, RENESAS TECHNOLOGY CORPORATIONInventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise