Patents by Inventor Yukinobu Miyamoto

Yukinobu Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741421
    Abstract: According to an embodiment, a semiconductor manufacturing apparatus includes a holder configured to hold a processing object, a heater provided at the holder and configured to heat the processing object, a first exhaust port provided above the holder and facing the holder, and an exhaust duct. The exhaust duct is provided on an outer side surface of the first exhaust port and includes an extension and contraction function.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: August 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takanori Fukusumi, Yukinobu Miyamoto
  • Publication number: 20190074200
    Abstract: According to an embodiment, a semiconductor manufacturing apparatus includes a holder configured to hold a processing object, a heater provided at the holder and configured to heat the processing object, a first exhaust port provided above the holder and facing the holder, and an exhaust duct. The exhaust duct is provided on an outer side surface of the first exhaust port and includes an extension and contraction function.
    Type: Application
    Filed: February 21, 2018
    Publication date: March 7, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Takanori FUKUSUMI, Yukinobu MIYAMOTO
  • Publication number: 20150227054
    Abstract: According to one embodiment, an EUV radiation exposure apparatus includes a vacuum chamber, an EUV radiation exposing light source installed in the vacuum chamber, and an ionizer that generates positive or negative ions. The ionizer is installed in the vacuum chamber and is driven with driving of the EUV radiation exposing light source.
    Type: Application
    Filed: May 16, 2014
    Publication date: August 13, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukinobu MIYAMOTO, Kazuo TAWARAYAMA
  • Patent number: 5745336
    Abstract: A semiconductor integrated circuit apparatus according to the present invention has a capacitor formed in such a manner that a ferroelectric thin film is formed after a MOS transistor has been formed on a substrate thereof, a ferroelectric thin film made of, for example, PbZrTiO.sub.3 or SrTiO.sub.3 or the like is formed into a columnar shape to form electrodes positioned in direct contact with the side wall portions of said columnar ferroelectric thin film and the top portion is removed.
    Type: Grant
    Filed: April 6, 1995
    Date of Patent: April 28, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Katsuaki Saito, Michio Ohue, Takuya Fukuda, JaiHo Choi, Yukinobu Miyamoto
  • Patent number: 5434742
    Abstract: A semiconductor integrated circuit apparatus according to the present invention has a capacitor formed in such a manner that a ferroelectric thin film is formed after a MOS transistor has been formed on a substrate thereof, a ferroelectric thin film made of, for example, PbZrTiO.sub.3 or SrTiO.sub.3 or the like is formed into a columnar shape to form electrodes positioned in direct contact with the side wall portions of said columnar ferroelectric thin film, and the top portion is removed.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: July 18, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Katsuaki Saito, Michio Ohue, Takuya Fukuda, JaiHo Choi, Yukinobu Miyamoto