Patents by Inventor Yukinobu Murao

Yukinobu Murao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7666763
    Abstract: This invention provides a substrate structure capable of controlling the threshold voltage of a MOS transistor independently of the substrate concentration and easily suppressing a short channel effect caused by reducing the channel length. A first nanosilicon film formed from nanosilicon grains having the same grain size is formed on a silicon oxide film on the surface of a silicon substrate. A silicon nitride film is formed on the first nanosilicon film. Then, a second nanosilicon film having an average grain size different from that of the first nanosilicon film is formed. A semiconductor circuit device is formed on a thus manufactured nanosilicon semiconductor substrate.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: February 23, 2010
    Assignee: Canon Anelva Corporation
    Inventors: Yukinobu Murao, Akira Kumagai, Yoichiro Numasawa
  • Patent number: 7589002
    Abstract: An oxygen- or nitrogen-terminated silicon nanocrystalline structure is formed on a silicon substrate by forming a silicon film of fine silicon crystals and amorphous silicon on a substrate, and oxidizing or nitriding the formed silicon film with ions and radicals formed from an oxidizing gas or a nitriding gas. The oxidizing or nitriding step comprises substeps of disposing the substrate provided with the silicon film in an oxidizing or nitriding gas atmosphere within a plasma treatment chamber, and then plasma-oxiziding or plasma-nitriding the substrate provided with the silicon film by applying a high frequency electric field to the oxidizing or nitriding gas atmosphere. The method allows the particle diameter of the oxygen- or nitrogen-terminated silicon nanocrystals to be regulated to an accuracy of 1 to 2 nm, the density thereof per unit area to be increased, and the silicon nanocrystalline structure to be produced easily and inexpensively.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: September 15, 2009
    Assignee: Anelva Corporation
    Inventors: Yoichiro Numasawa, Yukinobu Murao
  • Publication number: 20080296579
    Abstract: This invention provides a substrate structure capable of controlling the threshold voltage of a MOS transistor independently of the substrate concentration and easily suppressing a short channel effect caused by reducing the channel length. A first nanosilicon film formed from nanosilicon grains having the same grain size is formed on a silicon oxide film on the surface of a silicon substrate. A silicon nitride film is formed on the first nanosilicon film. Then, a second nanosilicon film having an average grain size different from that of the first nanosilicon film is formed. A semiconductor circuit device is formed on a thus manufactured nanosilicon semiconductor substrate.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicant: CANON ANELVA CORPORATION
    Inventors: YUKINOBU MURAO, AKIRA KUMAGAI, YOICHIRO NUMASAWA
  • Publication number: 20080230781
    Abstract: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof.
    Type: Application
    Filed: May 19, 2008
    Publication date: September 25, 2008
    Inventors: Yoichiro Numasawa, Yukinobu Murao
  • Publication number: 20070262307
    Abstract: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof.
    Type: Application
    Filed: July 16, 2007
    Publication date: November 15, 2007
    Inventors: Yoichiro Numasawa, Yukinobu Murao
  • Publication number: 20060276055
    Abstract: A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. Thereby, a silicon nanocrystalline structure can be formed on a silicon substrate by using a process of producing silicon integrated circuits with achieving high luminous efficiency, and terminating reliably with oxygen or nitrogen on the surface thereof.
    Type: Application
    Filed: August 22, 2003
    Publication date: December 7, 2006
    Inventors: Yoichiro Numasawa, Yukinobu Murao
  • Patent number: 6281536
    Abstract: A ferroelectric memory device includes a ferroelectric capacitance element formed through an insulating film on a semiconductor substrate. The ferroelectric capacitance element includes a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film. The upper electrode has a laminate structure which contains a conductive oxide layer of first metal which is connected with the ferroelectric film.
    Type: Grant
    Filed: April 7, 1999
    Date of Patent: August 28, 2001
    Assignee: NEC Corporation
    Inventors: Sota Shinohara, Kazushi Amanuma, Yukinobu Murao, Yuukoh Katoh, Tsuneo Takeuchi, Yoshihiro Hayashi
  • Patent number: 5518962
    Abstract: A semiconductor device formed at a substrate surface region is coated with a non-doped CVD silicon oxide film, and an interlayer insulating film composed of a BPSG film, a first ozone-TEOS NSG film and a second ozone-TEOS NSG film is formed on the silicon oxide film. The BPSG film has a thickness of not less than 50 nm but not greater than 200 nm, and is heat-treated at a temperature of not lower than 700.degree. C. but not higher than 800.degree. C. In addition, the first and second zone-TEOS NSG films are also heat-treated at a temperature of not lower than 700.degree. C. but not higher than 800.degree. C.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: May 21, 1996
    Assignee: NEC Corporation
    Inventor: Yukinobu Murao
  • Patent number: 5491108
    Abstract: A method which can markedly improve the flatness of a semiconductor integrated circuit device by forming selectively a layer insulating film on an underlying substrate having level differences is disclosed. First, a Ti--W alloy film is formed on a member which brings about level differences due to wirings or the like, then a PECVD silicon oxide film is formed followed by a plasma treatment using CF.sub.4 gas. Further, a silicon oxide film is deposited by atmospheric pressure CVD using ozone and tetraethoxysilane. Then, the surface is flattened by etchback using an organic SOG film, and a silicon oxide film is formed by plasma excited CVD.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: February 13, 1996
    Assignee: NEC Corporation
    Inventors: Mieko Suzuki, Tetsuya Homma, Yukinobu Murao, Takaho Tanigawa, Hiroki Koga