Patents by Inventor Yukinobu Watanabe

Yukinobu Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11817024
    Abstract: In the present invention, output circuits are connected to respective external terminals. Each output circuit includes an operational amplifier that outputs a current to one external terminal until a voltage of the external terminal becomes equal to a gradation voltage received by an input terminal thereof, and a disconnection detection circuit that detects whether a wiring connected to the one external terminal is disconnected or not. The disconnection detection circuit supplies a test voltage instead of the gradation voltage to the input terminal of the operational amplifier in a non-display period and measures a time period taken from then until the voltage of the one external terminal exceeds a reference voltage as a rise time. The disconnection detection circuit detects whether the wiring connected to the one external terminal is disconnected or not based on the rise time measured in one frame and the rise time measured in another frame.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: November 14, 2023
    Assignee: LAPIS TECHNOLOGY CO., LTD.
    Inventor: Yukinobu Watanabe
  • Patent number: 11756490
    Abstract: A display device which can suppress erroneous display of a display panel is provided. A source driver receives a serial data signal in which a preamble and video data of the display panel are alternately continuous via an interface from a display controller. The source driver controls timing of supply of a gate signal from a gate driver based on the video data included in the serial data signal, and supplies a gradation voltage signal which corresponds to the video data to a plurality of data lines of the display panel. The source driver has a detection portion which detects that the interface is in an unstable state, and a gate reset signal output portion which outputs a gate reset signal for stopping an operation of the gate driver when the unstable state of the interface is detected at the time of the supply of the video data.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: September 12, 2023
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Yukinobu Watanabe
  • Publication number: 20230230557
    Abstract: An interface circuit comprises a timing signal generating unit that generates a timing signal indicating a timing to switch between a data input period and a non-input period, a plurality of driver error detection circuits that detects an error in source drivers, a selector circuit that selects one of the driver error detection circuits in the non-input period and that outputs a driver error detection signal indicating an error detection result, an input error detection circuit that detects an input error of a data signal and outputs an input error detection signal indicating the result, an OR circuit that outputs an OR of the driver error detection signal and the input error detection signal, and a signal output unit connected to an output part of the OR circuit.
    Type: Application
    Filed: March 21, 2023
    Publication date: July 20, 2023
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Yukinobu WATANABE
  • Publication number: 20230134769
    Abstract: In the present invention, output circuits are connected to respective external terminals. Each output circuit includes an operational amplifier that outputs a current to one external terminal until a voltage of the external terminal becomes equal to a gradation voltage received by an input terminal thereof, and a disconnection detection circuit that detects whether a wiring connected to the one external terminal is disconnected or not. The disconnection detection circuit supplies a test voltage instead of the gradation voltage to the input terminal of the operational amplifier in a non-display period and measures a time period taken from then until the voltage of the one external terminal exceeds a reference voltage as a rise time. The disconnection detection circuit detects whether the wiring connected to the one external terminal is disconnected or not based on the rise time measured in one frame and the rise time measured in another frame.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 4, 2023
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Yukinobu WATANABE
  • Patent number: 11636820
    Abstract: An interface circuit comprises a timing signal generating unit that generates a timing signal indicating a timing to switch between a data input period and a non-input period, a plurality of driver error detection circuits that detects an error in source drivers, a selector circuit that selects one of the driver error detection circuits in the non-input period and that outputs a driver error detection signal indicating an error detection result, an input error detection circuit that detects an input error of a data signal and outputs an input error detection signal indicating the result, an OR circuit that outputs an OR of the driver error detection signal and the input error detection signal, and a signal output unit connected to an output part of the OR circuit.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: April 25, 2023
    Assignee: LAPIS TECHNOLOGY CO., LTD.
    Inventor: Yukinobu Watanabe
  • Publication number: 20220328014
    Abstract: A display device which can suppress erroneous display of a display panel is provided. A source driver receives a serial data signal in which a preamble and video data of the display panel are alternately continuous via an interface from a display controller. The source driver controls timing of supply of a gate signal from a gate driver based on the video data included in the serial data signal, and supplies a gradation voltage signal which corresponds to the video data to a plurality of data lines of the display panel. The source driver has a detection portion which detects that the interface is in an unstable state, and a gate reset signal output portion which outputs a gate reset signal for stopping an operation of the gate driver when the unstable state of the interface is detected at the time of the supply of the video data.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 13, 2022
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Yukinobu Watanabe
  • Patent number: 11455939
    Abstract: An interface circuit generates a timing signal indicating the timing at which to switch between a data input period and a non-input period, and outputs a second start pulse signal obtained by delaying a first start pulse signal. Anomaly detection circuits detect an anomaly that has occurred in source drivers, and a detection result selection circuit selects one of the anomaly detection circuits during the non-input period and outputs a detection result signal indicating detection results. A selector selectively outputs the second start pulse signal or the detection result signal on the basis of the timing signal.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: September 27, 2022
    Assignee: LAPIS TECHNOLOGY CO., LTD.
    Inventor: Yukinobu Watanabe
  • Patent number: 11393409
    Abstract: A display device which can suppress erroneous display of a display panel is provided. A source driver receives a serial data signal in which a preamble and video data of the display panel are alternately continuous via an interface from a display controller. The source driver controls timing of supply of a gate signal from a gate driver based on the video data included in the serial data signal, and supplies a gradation voltage signal which corresponds to the video data to a plurality of data lines of the display panel. The source driver has a detection portion which detects that the interface is in an unstable state, and a gate reset signal output portion which outputs a gate reset signal for stopping an operation of the gate driver when the unstable state of the interface is detected at the time of the supply of the video data.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: July 19, 2022
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Yukinobu Watanabe
  • Publication number: 20220172668
    Abstract: An interface circuit generates a timing signal indicating the timing at which to switch between a data input period and a non-input period, and outputs a second start pulse signal obtained by delaying a first start pulse signal. Anomaly detection circuits detect an anomaly that has occurred in source drivers, and a detection result selection circuit selects one of the anomaly detection circuits during the non-input period and outputs a detection result signal indicating detection results. A selector selectively outputs the second start pulse signal or the detection result signal on the basis of the timing signal.
    Type: Application
    Filed: November 18, 2021
    Publication date: June 2, 2022
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Yukinobu WATANABE
  • Publication number: 20220172689
    Abstract: An interface circuit comprises a timing signal generating unit that generates a timing signal indicating a timing to switch between a data input period and a non-input period, a plurality of driver error detection circuits that detects an error in source drivers, a selector circuit that selects one of the driver error detection circuits in the non-input period and that outputs a driver error detection signal indicating an error detection result, an input error detection circuit that detects an input error of a data signal and outputs an input error detection signal indicating the result, an OR circuit that outputs an OR of the driver error detection signal and the input error detection signal, and a signal output unit connected to an output part of the OR circuit.
    Type: Application
    Filed: November 18, 2021
    Publication date: June 2, 2022
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Yukinobu WATANABE
  • Publication number: 20200294453
    Abstract: A display device which can suppress erroneous display of a display panel is provided. A source driver receives a serial data signal in which a preamble and video data of the display panel are alternately continuous via an interface from a display controller. The source driver controls timing of supply of a gate signal from a gate driver based on the video data included in the serial data signal, and supplies a gradation voltage signal which corresponds to the video data to a plurality of data lines of the display panel. The source driver has a detection portion which detects that the interface is in an unstable state, and a gate reset signal output portion which outputs a gate reset signal for stopping an operation of the gate driver when the unstable state of the interface is detected at the time of the supply of the video data.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 17, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Yukinobu Watanabe
  • Patent number: 10134347
    Abstract: A display driver includes a driving voltage generation part that generates a voltage as a pixel driving voltage by inverting a polarity of a voltage representing a luminance level of each pixel based on a video signal according to a polarity inversion signal received via a transmission line, the polarity inversion signal alternately indicating either one of positive and negative polarities, and a polarity inversion abnormality detection part that generates an abnormality detection signal indicating an abnormality of the transmission line when the polarity inversion signal indicates only one constant polarity for a period of N frames (N is an integer greater than or equal to 2) of the video signal.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: November 20, 2018
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Yukinobu Watanabe
  • Publication number: 20180068623
    Abstract: A display driver includes a driving voltage generation part that generates a voltage as a pixel driving voltage by inverting a polarity of a voltage representing a luminance level of each pixel based on a video signal according to a polarity inversion signal received via a transmission line, the polarity inversion signal alternately indicating either one of positive and negative polarities, and a polarity inversion abnormality detection part that generates an abnormality detection signal indicating an abnormality of the transmission line when the polarity inversion signal indicates only one constant polarity for a period of N frames (N is an integer greater than or equal to 2) of the video signal.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 8, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Yukinobu WATANABE
  • Patent number: 9602124
    Abstract: An A/D conversion device includes: a level shifter circuit configured to level-shift an analog voltage of an input voltage signal to generate a conversion signal; an A/D converter configured to A/D-convert a voltage of the conversion signal supplied from the level shifter circuit. The level shifter circuit subtracts an instantaneous voltage value of the input voltage signal from a reference voltage so as to output a signal value as the conversion signal.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: March 21, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Yukinobu Watanabe
  • Patent number: 9495925
    Abstract: A display device includes display panel includes a first source driver including a first input terminal and a first output terminal connected to the display panel; a first gate driver including a first input-output terminal, a second input-output terminal connected to the first input-output terminal, and a second output terminal connected to the display panel; a timing controller including a first terminal for outputting or inputting a first signal to or from the first input-output terminal and a second terminal; a first signal line connected to the first terminal; a second signal line connected to the second terminal; and a third signal line connected to the first source driver and the timing controller for transmitting a second signal indicating a display direction of the image data. The first source driver operates according to the first signal from the first terminal or the second terminal selected.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: November 15, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Yukinobu Watanabe, Yuichi Matsushita
  • Publication number: 20160248436
    Abstract: An A/D conversion device includes: a level shifter circuit configured to level-shift an analog voltage of an input voltage signal to generate a conversion signal; an A/D converter configured to A/D-convert a voltage of the conversion signal supplied from the level shifter circuit. The level shifter circuit subtracts an instantaneous voltage value of the input voltage signal from a reference voltage so as to output a signal value as the conversion signal.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 25, 2016
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Yukinobu WATANABE
  • Publication number: 20160093245
    Abstract: When an amplifier supplies to a drive line a driving signal based on an input voltage corresponding to a data value indicated by input data, and feeds to an output line a current corresponding to a voltage value on the drive line, the amplifier precharges the drive line at start of increase or decrease of the input voltage. Furthermore, the amplifier stops the precharge when the data value indicated by the input data is smaller than a reference value, or when a difference between a data value at present and a data value immediately therebefore in a series of data values indicated by the input data is smaller than a reference difference value.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 31, 2016
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Yukinobu WATANABE
  • Publication number: 20140375625
    Abstract: A display device includes display panel includes a first source driver including a first input terminal and a first output terminal connected to the display panel; a first gate driver including a first input-output terminal, a second input-output terminal connected to the first input-output terminal, and a second output terminal connected to the display panel; a timing controller including a first terminal for outputting or inputting a first signal to or from the first input-output terminal and a second terminal; a first signal line connected to the first terminal; a second signal line connected to the second terminal; and a third signal line connected to the first source driver and the timing controller for transmitting a second signal indicating a display direction of the image data. The first source driver operates according to the first signal from the first terminal or the second terminal selected.
    Type: Application
    Filed: June 9, 2014
    Publication date: December 25, 2014
    Inventors: Yukinobu WATANABE, Yuichi MATSUSHITA
  • Patent number: 5131302
    Abstract: Disclosed herein is an automatic toilet paper supplier. The supplier includes portions for holding in rotatable fashion a toilet paper roll. The roll is located to unwind between two rollers which are driven by a time activated motor. After passing through the rollers, the paper passes into a cutter which is also driven by a time activated motor. Here the paper is cut to slide down a guide means into an adjustable receiving means where it folds upon itself.
    Type: Grant
    Filed: August 30, 1989
    Date of Patent: July 21, 1992
    Inventor: Yukinobu Watanabe
  • Patent number: 4520338
    Abstract: Cylindrical fuses in which, when overcurrent flows to an electric circuit, the part of the electric circuit formed by metal having a low melting point is fused to maintain safety of various electric machinery and equipment.The cylindrical fuse includes a cylindrical or bar like insulator formed of glass, porcelain, ceramics, plastics and the like and metals having a low melting point which are adhered to the cylindrical or bar like insulator by means of printing, coating, electroplating and the like, for example, lead or an alloy of lead and tin. A fuse terminal to be formed at both ends or one end of the cylindrical or bar like insulator and a fuse portion formed continuously between and connecting the fuse terminals are formed by the adhesion of the metals of low melting points.
    Type: Grant
    Filed: July 7, 1983
    Date of Patent: May 28, 1985
    Inventor: Yukinobu Watanabe